Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments with respect to the newly amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments regarding Claim 1 have been considered. Applicant contends that neither Im nor Kim teaches or suggests a landing pad extending onto and directly contacting the first surface of the first encapsulation layer. However, this argument is no longer persuasive in view of the modification of the rejection under 35 U.S.C. 103. While Im may not explicitly illustrate this specific landing pad configuration, Ng explicitly teaches bonding wires (302) connected to landing pads (321) on a substrate (320) that extend onto and directly contact the encapsulant layer (330) surface. Modifying Im’s package with the landing pads of Ng represents a routine design combination to ensure reliable electrical interconnections. Furthermore, this new ground of rejection under 35 U.S.C. 103 was necessitated by Applicant's claim amendments adding structural features not previously claimed, rendering this Office Action properly Final under MPEP § 706.07(a).
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s)1-2, 4-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Im et al. (US 20180269126 A1) in view of Ng et al. (US 10312219 B2).
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CLAIM 1: Im teaches a semiconductor package comprising:
a semiconductor chip 120;
a bonding wire 128 connected to the semiconductor chip 120;
a first encapsulation layer 130 surrounding the bonding wire 128; and
a second encapsulation layer 140 surrounding the first encapsulation layer, a surface roughness of the first encapsulation layer 130 being less than that of the second encapsulation layer 140 (Im ¶1021); and
a landing pad contacting the bonding wire (The landing pad contacting he bonding wire 128 is inherent in the disclosure of Im Fig. 7f. The bonding wire 128 must necessarily terminate at a conductive landing pad or terminal on the substrate 110 to establish a electrical and mechanical connection; a bonding wire cannot function or be secured in the manner shown without such contact point.);
Im does not explicitly show a landing pad contacting the bonding wire, wherein the landing pad extends onto and directly contacts the first surface of the first encapsulation layer.
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Ng teaches a semiconductor device assembly comprising a substrate 320, bonding wires 302 connected to semiconductor dies, an encapsulant layer 330, and conductive landing pads/external connections 321 disposed on the substrate 320 contacting the bonding wires 302, wherein the landing pads 321 extend onto and directly contact the surface of the encapsulant layer 330 (Ng Fig. 3, elements 302, 320, 321, 330).
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the semiconductor package of Im to incorporate the landing pads extending onto and directly contacting the surface of the first encapsulation layer as taught by Ng, in order to provide secure mechanical support and reliable electrical contact for the wire bonds terminating at the carrier substrate, since applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 2. Im in view of Ng teaches a semiconductor package according to claim 1, wherein the first encapsulation layer includes a first surface that has a first roughness, and wherein the second encapsulation layer includes a second surface that has a second roughness, the first roughness less than the second roughness (Im Fig. 7f & ¶102).
CLAIM 4. Im in view of Ng teaches a semiconductor package according to claim 1, wherein the first surface, the second surface and one surface of the bonding wire are formed in substantially the same plane (The first encapsulation layer 130, second encapsulation layer 140, and bonding wire 128 are each seated on and share a common plane at the chip surface 120s.)
CLAIM 5. Im in view of Ng teaches a semiconductor package according to claim 1, further comprising: an insulating layer on the first surface and the second surface, wherein the landing pad is disposed in the insulating layer, and wherein one surface of the insulating layer directly contacts the first surface and the second surface ().
CLAIM 6. Im in view of Ng teaches a semiconductor package according to claim 1, wherein the first encapsulation layer includes first resin and first fillers, wherein the second encapsulation layer includes second resin and second fillers, and wherein an average size of the first fillers is less than that of the second fillers (Im ¶100-102 – Fillers (e.g. particles - Particle volume and size as disclosed directly corresponds to surface roughness. As such, smaller particles would be associated with the smaller surface roughness.).
CLAIM 7. Im in view of Ng teaches a semiconductor package according to claim 1, wherein the first encapsulation layer includes first resin and first fillers, wherein the second encapsulation layer includes second resin and second fillers, and wherein a volume ratio of the first fillers in the first encapsulation layer is less than a volume ratio of the second fillers in the second encapsulation layer (Im ¶100-102 – Fillers (e.g. particles - Particle volume and size as disclosed directly corresponds to surface roughness. As such, smaller particles would be associated with the smaller surface roughness.).
CLAIM 8. Im in view of Ng teaches a semiconductor package according to claim 1, wherein the first encapsulation layer includes any combination of a wire coating material, an underfill 180 (¶141), a die attach film (DAF) 126, a film over wire (FOW), an epoxy molding compound (Im Fig. 7f & ¶102).
CLAIM 12. IM in view of Kim teach a semiconductor package according to claim 1, wherein the second encapsulation layer includes an epoxy molding compound (Im Fig. 7f & ¶102).
CLAIM 10. Im in view of Ng teaches a semiconductor package according to claim 1, wherein the semiconductor chip includes a chip terminal, and wherein the bonding wire overlaps the chip terminal (The landing pad contacting he bonding wire 128 is inherent in the disclosure of Im Fig. 7f. The bonding wire 128 must necessarily terminate at a conductive landing pad or terminal on the substrate)
CLAIM 11. Im in view of Ng teaches a semiconductor package according to claim 10, wherein the landing pad overlaps the bonding wire (The landing pad contacting he bonding wire 128 is inherent in the disclosure of Im Fig. 7f. The bonding wire 128 must necessarily terminate at a conductive landing pad or terminal on the substrate)
CLAIM 12. Im in view of Ng teaches a semiconductor package comprising: a semiconductor chip 120; a connecting interconnection connected to the semiconductor chip (The landing pad contacting he bonding wire 128 is inherent in the disclosure of Im Fig. 7f. The bonding wire 128 must necessarily terminate at a conductive landing pad or terminal on the substrate); a first encapsulation layer 130 surrounding the connecting interconnection 128; a second encapsulation layer 140 surrounding the first encapsulation layer 130, a surface roughness of the first encapsulation layer less than a surface roughness of the second encapsulation layer & ¶102); and a landing pad contacting the connecting interconnection, wherein a plurality of the connecting interconnections includes any combination of a vertical wire 128, a conductive pillar, a conductive bump (Im Fig. 7f – Note Im figs 1-19E further depict various conventional wiring connections including vertical connection such as pillars and bumps.)
Im does not explicitly show a landing pad contacting the bonding wire, wherein the landing pad extends onto and directly contacts the first surface of the first encapsulation layer.
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Ng teaches a semiconductor device assembly comprising a substrate 320, bonding wires 302 connected to semiconductor dies, an encapsulant layer 330, and conductive landing pads/external connections 321 disposed on the substrate 320 contacting the bonding wires 302, wherein the landing pads 321 extend onto and directly contact the surface of the encapsulant layer 330 (Ng Fig. 3, elements 302, 320, 321, 330).
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the semiconductor package of Im to incorporate the landing pads extending onto and directly contacting the surface of the first encapsulation layer as taught by Ng, in order to provide secure mechanical support and reliable electrical contact for the wire bonds terminating at the carrier substrate, since applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220059503 A1) in view of Im et al. (US 20180269126 A1) in view of Ng et al. (US 10312219 B2
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CLAIM 13. Kim et al. teaches in Figure 8B semiconductor package comprising:
a chip stack 510 including a plurality of semiconductor chips 510 stacked and offset from each other;
a copper pillar bump 521A/515A (Kim ¶31 – wiring, bumps, conductive lines are formed of conventional metals such as copper. It’s a known obvious selection to a PHOSITA for intended use.) connected to one semiconductor chip 510 disposed at an uppermost layer among the plurality of semiconductor chips;
a plurality of vertical wires 520A connected to remaining semiconductor chips except the one semiconductor chip disposed at the uppermost layer among the plurality of semiconductor chips;
a first encapsulation layer 530 adjacent to the plurality of vertical wires and the copper pillar bump; and a plurality of landing pads 544L on the plurality of vertical wires and the copper pillar bump 521A 515A (Kim ¶31 – wiring, bumps, conductive lines are formed of conventional metals such as copper. It’s a known obvious selection to a PHOSITA for intended use.).
Kim et al. is silent upon a second encapsulation layer disposed on a side surface of the first encapsulation layer, a surface roughness of the first encapsulation layer less than a surface roughness of the second encapsulation layer.
Im teaches the known option of encapsulating a chip package with a first and second encapsulating material. Specifically, Im teaches that encapsulating the wiring separately may prevent movement of the wire bonds. Further, as taught in Im, filler particles may be included in he encapsulation materials. Im discloses that smaller particles in the encapsulating materials that surround the wire bonding, and larger filler particles in the second encapsulant, serve purposes such as greater heat transfer. Smaller particles result in a smaller surface roughness that the second encapsulant with larger filler particles.
It would have been obvious to a PHOSITA at the time of the invention to modify the package of Kim to include a second encapsulation layer disposed on a side surface of the first encapsulation layer, with a surface roughness of the first encapsulation layer being less than that of the second encapsulation layer. A PHOSITA would have been motivated to incorporate the dual-layer encapsulation taught by Im (Im Fig. 7F & ¶102) into the device of Kim because applying a known technique to a known device ready for improvement to yield predictable results is considered obvious.
Specifically, the optimization of encapsulant at specific locations within a package provides the predictable benefits of preventing wire sweeping via the first encapsulant and providing heat transfer via the second encapsulant. Such a modification represents the use of known elements according to known methods to yield predictable results (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Regarding wherein the plurality of landing pads extends onto and directly contacts the first surface of the first encapsulation layer, Fig. 8B as applied above may not clearly show the landing pads extending onto and directly contacting the surface of the encapsulation layer as the pads appear small than that of the wire end portion. However as shown in figure 6A, the pads may not be fully align on the wire end, thereby having pads which meet the broad scope of the claim limitation. Further, as shown on the opposing surface of the encapsulation, pads may also be clearly larger and be on and contacting the surface.
Additionally, Im does not explicitly show a landing pad contacting the bonding wire, wherein the landing pad extends onto and directly contacts the first surface of the first encapsulation layer.
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Ng teaches a semiconductor device assembly comprising a substrate 320, bonding wires 302 connected to semiconductor dies, an encapsulant layer 330, and conductive landing pads/external connections 321 disposed on the substrate 320 contacting the bonding wires 302, wherein the landing pads 321 extend onto and directly contact the surface of the encapsulant layer 330 (Ng Fig. 3, elements 302, 320, 321, 330).
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the semiconductor package of Im and or Kim to incorporate the landing pads extending onto and directly contacting the surface of the first encapsulation layer as taught by Ng and also demonstrated on the opposing surface in figure 6a of Kim, in order to provide secure mechanical support and reliable electrical contact for the wire bonds terminating at the carrier substrate, since applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 14. Kim in view of Im in view of Ng teach a semiconductor package according to claim 13, wherein the semiconductor package further comprises an insulating layer directly contacting the first surface and the second surface (Kim as modified by Im Fig. 7 & ¶102 – Im teaches the use of 1st and 2nd encapsulants having the relative surface roughness’s and being insulative.).
CLAIM 15. Kim in view of Im in view of Ng teach a semiconductor package according to claim 13, wherein a lowermost end of the first encapsulation layer is provided at a level lower than a top surface of the semiconductor chip disposed at the uppermost layer among the plurality of semiconductor chips (Kim as modified by Im Fig. 7 & ¶102 – Applying the first encapsulant to the stacked package of Kim to encapsulate the wire bonds will result in the recited relative arrangement.).
CLAIM 16. Kim in view of Im in view of Ng teach a semiconductor package according to claim 15, wherein a lowermost end of the first encapsulation layer is provided at a level higher than a top surface of one semiconductor chip disposed at a lowermost end among the plurality of semiconductor chips (Kim as modified by Im Fig. 7 & ¶102 – Applying the first encapsulant to the stacked package of Kim to encapsulate the wire bonds will result in the recited relative arrangement.).
CLAIM 17. Kim in view of Im teach a semiconductor package according to claim 15, wherein a lowermost end of the first encapsulation layer is provided at a level higher than a bottom surface of one semiconductor chip disposed at an uppermost end among the plurality of semiconductor chips (Kim as modified by Im Fig. 7 & ¶102 – Applying the first encapsulant to the stacked package of Kim to encapsulate the wire bonds will result in the recited relative arrangement.).
CLAIM 18. Kim in view of Im in view of Ng teach a semiconductor package according to claim 13, wherein the second encapsulation layer surrounds a side surface of the first encapsulation layer (Kim as modified by Im Fig. 7 & ¶102 – Applying the first encapsulant to the stacked package of Kim to encapsulate the wire bonds will result in the recited relative arrangement.).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220059503 A1) in view of Im et al. (US 20180269126 A1) in view of Ng et al. (US 10312219 B2) in view of Kumar et al. (US 20150228621 A1)
CLAIM 19. Kim in view of Im in view of Ng teach a semiconductor package according to claim 13, wherein the plurality of semiconductor chips comprise: a first semiconductor chip 510A; a second semiconductor chip stacked 510B on the first semiconductor chip offset in a first direction (Kim et al. Fig. 8B);
Kim is may be silent upon disclosing the capability of stacking additional chip stacks such that the package may include a third semiconductor chip stacked on the second semiconductor chip offset in the first direction; and a fourth semiconductor chip stacked on the third semiconductor chip offset in a second direction different from the first direction.
Kumar demonstrates in Fig. 12 stacking at least four chip stacks was a known option at the time of the invention to a PHOSITA.
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It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the stack of Kim as modified by Im with third and fourth stacks as demonstrated in Kumar, since applying a known technique (duplication of parts) to a known device ready for improvement (ship stacking) to yield predictable results (increased complexity (i.e. increased memory, etc.. ) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/10/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Im et al. - ¶[0102] For example, the top surface 120s of the semiconductor chip 120 in direct contact with the heat dissipation layer 140 may be an uneven surface with a first surface roughness. The top surface 130s of the mold layer 130 in direct contact with the heat dissipation layer 140 may be an uneven surface with a second surface roughness. The semiconductor chip 120 may be mainly formed of silicon and the mold layer 130 may be formed of an epoxy resin, and in this case, the first surface roughness may be smaller than the second surface roughness.
Prosecution Insights