DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Amendment
Acknowledgment is made of applicant's Amendment, filed 01-14-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 1, 10 and 18 has/have been amended, claim(s) 8 and 15 has/have been cancelled, and claim(s) 1-7, 9-14, and 16-20 remain(s) pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 9-14, 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, US 20200006646 A1, in view of Chang, US 20240389486 A1.
As to claim 1, Cheng discloses a memory device (see Cheng Para [0002]) comprising:
a first electrode (see Cheng Fig 8A Ref 12) and a second electrode (see Cheng Fig 8A Ref 30) spaced apart from each other; and
a memory layer (see Cheng Fig 8 layers between Refs 12 and 30) between the first electrode and the second electrode, the memory layer including a plurality of memory material layers (see Cheng Fig 8A Refs 20R, 24R, and 28R) having different threshold voltages from each other (see Cheng Para [0059]; There is a different voltage required to produce the described currents for each of the layers.), wherein
each of the plurality of memory material layers includes a chalcogenide-based material (see Cheng Para [0059]), and a resistivity varying with a polarity and an intensity of an applied voltage (see Cheng Para [0059]).
Cheng does not appear to explicitly disclose
has an ovonic threshold switching (OTS) characteristic, and is configured to have a threshold voltage, and
when a number of the plurality of memory materials layers is n, 2*(n+1) level states are implemented.
Chang discloses
has an ovonic threshold switching (OTS) characteristic, and is configured to have a threshold voltage (see Chang Para [0019]), and
when a number of the plurality of memory materials layers is n, 2*(n+1) level states are implemented (see Chang Para [0019]; Chang discloses the same number of possible resistance states, as understood by the disclosure of the specification in paragraph [0088].).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a device, as disclosed by Cheng, may implement particular phase change devices, with particular chemistries, for particular applications, as disclosed by Chang. The inventions are well known variants of phase change memory technologies, and the combinations of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Chang’s attempt to tailor electrical characteristics for circuits (see Chang Para [0019]).
As to claim 2, Cheng and Chang disclose the memory device of claim 1, wherein
each of the plurality of memory material layers includes a chalcogen element including at least one of Se and Te (see Cheng Paras [0055] and [0059]), and at least one of Ge, As, or Sb (see Cheng Paras [0055] and [0059]).
As to claim 3, Cheng and Chang disclose the memory device of claim 2, wherein
at least one of the plurality of memory material layers further includes at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, P, or S (see Chang Para [0054]).
As to claim 4, Cheng and Chang disclose the memory device of claim 1, wherein
the plurality of memory material layers have different threshold voltages (see Chang Para [0019]) from each other according to a composition or the composition and a thickness thereof (see Chang Para [0054]).
As to claim 5, Cheng and Chang disclose the memory device of claim 1, wherein
the plurality of memory material layers perpendicularly to the first and second electrodes and are electrically connected to one another in parallel (see Cheng Fig 8 layers between Refs 12 and 30).
As to claim 6, Cheng and Chang disclose the memory device of claim 5, wherein
the plurality of memory material layers are in parallel to each other when in a plan view (see Cheng Fig 8B).
As to claim 7, Cheng and Chang disclose the memory device of claim 5, wherein
the plurality of memory material layers are in concentric circles when in a plan view (see Cheng Fig 8B).
As to claim 9, Cheng and Chang disclose the memory device of claim 1, wherein
each of the plurality of memory material layers is configured to implement a low-threshold voltage state and a high-threshold voltage state using writing voltage pulses of different polarities (see Cheng Fig 9A).
As to claim 10, Cheng and Chang disclose a memory device (see Cheng Para [0002]) comprising:
a plurality of memory cells (see Cheng Para [0002]; NVRAM has a plurality of cells.), with each of the plurality of memory cells comprising a first electrode (see Cheng Fig 8A Ref 12) and a second electrode (see Cheng Fig 8A Ref 30) spaced apart from each other; and a memory layer (see Cheng Fig 8 layers between Refs 12 and 30) between the first electrode and the second electrode, the memory layer including a plurality of memory material layers (see Cheng Fig 8A Refs 20R, 24R, and 28R) having different threshold voltages (see Cheng Para [0059]) from each other such that, when a number of the plurality of memory materials layers is n, 2*(n+1) level states are implemented (see Chang Para [0019]; Chang discloses the same number of possible resistance states, as understood by the disclosure of the specification in paragraph [0088].), wherein
each of the plurality of memory material layers includes a chalcogenide-based material (see Cheng Para [0059]), has an ovonic threshold switching (OTS) characteristic (see Chang Para [0019]), and is configured to have a threshold voltage (see Chang Para [0019]) varying with a polarity and an intensity of an applied voltage (see Cheng Para [0059]).
As to claim 11, Cheng and Chang disclose the memory device of claim 10.
Claim 11 recites substantially the same limitations as claim 2.
All the limitations of claim 11 have already been disclosed by Cheng and Chang in claim 2 above.
As to claim 12, Cheng and Chang disclose the memory device of claim 11.
Claim 12 recites substantially the same limitations as claim 3.
All the limitations of claim 12 have already been disclosed by Cheng and Chang in claim 3 above.
As to claim 13, Cheng and Chang disclose the memory device of claim 10.
Claim 13 recites substantially the same limitations as claim 4.
All the limitations of claim 13 have already been disclosed by Cheng and Chang in claim 4 above.
As to claim 14, Cheng and Chang disclose the memory device of claim 10.
Claim 14 recites substantially the same limitations as claim 5.
All the limitations of claim 14 have already been disclosed by Cheng and Chang in claim 5 above.
As to claim 16, Cheng and Chang disclose the memory device of claim 10.
Claim 16 recites substantially the same limitations as claim 9.
All the limitations of claim 16 have already been disclosed by Cheng and Chang in claim 9 above.
As to claim 20, Cheng and Chang disclose an electronic apparatus (see Cheng Para [0002]) comprising the memory device of claim 10.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, US 20200006646 A1 and Chang, US 20240389486 A1, in view of Nardi, US 20200303459 A1.
As to claim 17, Cheng and Chang disclose the memory device of claim 10, further comprising:
a lines extending in a first direction (see Chang Fig 4D Ref 678)
Cheng and Chang do not appear to explicitly disclose
a plurality of bit lines extending in a first direction, and a plurality of word lines extending in a second direction crossing the first direction, wherein
the plurality of memory cells are respectively provided at points where the plurality of bit lines and the plurality of word lines cross each other.
Nardi discloses
a plurality of bit lines extending in a first direction (see Nardi Fig 2 Ref 206), and a plurality of word lines extending in a second direction crossing the first direction (see Nardi Fig 2 Ref 208), wherein
the plurality of memory cells are respectively provided at points where the plurality of bit lines and the plurality of word lines cross each other (see Nardi Fig 2 Ref 200).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a device, as disclosed by Cheng and Chang, may implement interconnect structure, as disclosed by Nardi. The inventions are well known variants of phase change memory technologies, and the combinations of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Nardi’s attempt to improve stability through interconnects (see Nardi Para [0022]).
As to claim 18, Cheng, Chang, and Nardi disclose the memory device of claim 10, further comprising:
a plurality of word planes that extend along a plane including a first direction and a second direction (see Nardi Fig 7A Ref WL) and spaced apart from each other in a third direction (see Nardi Fig 7A Ref WL), and a vertical bit line passing through the plurality of word planes and extending in the third direction (see Nardi Fig 7A Ref BVL), wherein
the memory layer is between the vertical bit line and each of the word planes (see Nardi Fig 7A Ref 701).
As to claim 19, Cheng, Chang, and Nardi disclose the memory device of claim 18,
plurality of memory material layers are stacked in the third direction (see Nardi Fig 7A Refs 701 and 703).
Response to Arguments
Applicant's arguments filed 01/14/2026 have been fully considered but they are not persuasive.
Cheng is relied upon for a multi-memory layer structure in a single stack, and Chang is relied upon to teach multi-level reading/writing, thus the arguments are directed to the wrong prior art.
The embodiment relied upon in Cheng (Cheng Figure 8A) implements individual discrete memory layers with different compositions, as disclosed in Cheng paragraph [0053], and Chang discloses a memory device implements individual discrete memory layers with different threshold voltages to enable a particular I-V response, as disclosed in Chang paragraph [0104]. Multi-state memory devices are not limited by the number of memory layers implemented in the particular memory device, but the sensitivity of the read out circuity.
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Figure 9A of Cheng has been amended about to show how inherently, the device disclosed by Cheng may implement thresholds to create an 2*(n+1) level schema. Cheng is not optimized for such operations however, and Chang, which does optimize such read outs for a similar memory structure, was combined with Cheng, to make obvious the claimed limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 02/24/2026