DETAILED ACTION
Examiner’s Note
Below prior art cited in PTO-892 but not used in the current rejection can also be used to reject the claims:
LAN; Wen-Ting et al. (US 20220173213 A1), (element 122 is isolation structure, element 150 is dielectric fin structure).
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Claim Notes
The specification including claims use the limitataion ‘dielectric fin structure’ and element 119 in the applicant’s drawings is mentioned as fin. However, ‘fin’ in semiconductor world is used to indicate a thin, vertical strip formed on the substrate. Applicant’s element 108 is a fin. However, element 119 doesn’t look like a fin, rather the shape and the location of element 119 is similar to an interlayer dielectric layer. Thus, no patentable weight will be given on the limitataion ‘fin’ in ‘dielectric fin structure’.
Election/Restrictions
Applicant’s election without traverse of Invention I (semiconductor device) I, species B/figs. 69-85, reflected in claims 1-15, 21-25 in the reply filed on 07/30/2026 is acknowledged. Claims 16-20 are cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 10, 12, 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (US 20190006486 A1, hereinafter Ching’486).
Regarding independent claim 1, Ching’486 teaches, “A semiconductor structure (fig. 1-14; ¶ [0001] - ¶ [0069]), comprising:
a channel structure (110/210, fig. 2A, 14C) on a substrate (100), wherein the channel structure (110/210) extends along a first direction;
a dielectric fin structure (125/145, fig. 5A, fig. 14C) on the substrate (100) and adjacent to the channel structure (210),
wherein the dielectric fin structure (145/125) comprises a stiff dielectric material (¶ [0036]) and extends along a second direction parallel to the first direction; and
an isolation structure (140, fig. 5A) extending through the channel structure, wherein the isolation structure (140) is in contact with the dielectric fin structure (125)”.
Regarding independent claim 10, Ching’486 teaches, “A semiconductor device (fig. 1-14; ¶ [0001] - ¶ [0069]), comprising:
a plurality of channel structures (110/210, figs. 2A, 10A, 14C) on a substrate (100);
a plurality of dielectric fin structures (125/145, figs. 5A, 10A, 14C) comprising a stiff dielectric material (¶ [0036]) on the substrate (100),
wherein the plurality of channel structures (figs. 7C, 11C) and the plurality of dielectric fin structures are arranged in an alternate configuration;
a gate structure (230, fig. 12A) surrounding the plurality of channel structures and the plurality of dielectric fin structures; and
an isolation structure (140, fig. 5A) extending through the gate structure (230, fig. 12A) and at least one of the plurality of channel structures (110), wherein the isolation structure (140, fig. 5A) is in contact with the at least one of the plurality of dielectric fin structures (125)”.
Regarding independent claim 21, Ching’486 teaches, “A semiconductor device (fig. 1-14; ¶ [0001] - ¶ [0069]), comprising:
first and second channel structures (110/210, figs. 2A, 10A, 14C) on a substrate (100);
a dielectric fin structure (125/145, figs. 5A, 10A, 14C) comprising a stiff dielectric material (¶ [0036]) on the substrate (100), wherein dielectric fin structure is between the first and second channel structures;
a gate structure (230, fig. 12A) on the first and second channel structures and the dielectric fin structure; and
an isolation structure (140, fig. 5A) extending through the gate structure and the second channel structure,
wherein the isolation structure (140, fig. 5A) is in contact with the dielectric fin structure (125)”.
Regarding claim 3, Ching’486 further teaches, “The semiconductor structure of claim 1, further comprising a gate structure (180, figs. 11A-11C) wrapped around the channel structure (210), wherein the gate structure (210) is between the channel structure (210) and the dielectric fin structure (145)”.
Regarding claim 4, 12 and 23, Ching’486 further teaches, “The semiconductor structure of claim 3, wherein a top surface of the dielectric fin structure (145) is below a top surface of the gate structure (180)”.
Regarding claim 5, Ching’486 further teaches, “The semiconductor structure of claim 3, wherein a ratio of a height of the isolation structure to a height of the gate structure ranges from about 0.15 to about 0.3 (fig. 10A)”.
Claims 1-2, 6-11, 13-15, 21-22 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 20210376072 A1, hereinafter Yu’072).
Regarding independent claim 1, Yu’072 teaches, “A semiconductor structure (fig. 1-34; ¶ [0001] - ¶ [0070]), comprising:
a channel structure (206, fig. 34A-D) on a substrate (202), wherein the channel structure (206) extends along a first direction;
a dielectric fin structure (212, 292) on the substrate (202) and adjacent to the channel structure (206),
wherein the dielectric fin structure (212, 292) comprises a stiff dielectric material (¶ [0027]) and extends along a second direction parallel to the first direction; and
an isolation structure (282, 284) extending through the channel structure (206), wherein the isolation structure (282, 284) is in contact with the dielectric fin structure (212, 292)”.
Regarding independent claim 10, Yu’072 teaches, “A semiconductor device (fig. 1-34; ¶ [0001] - ¶ [0070]), comprising:
a plurality of channel structures (206, fig. 34A-D) on a substrate (202);
a plurality of dielectric fin structures (212, 292) comprising a stiff dielectric material (¶ [0027]) on the substrate (202),
wherein the plurality of channel structures (2096) and the plurality of dielectric fin structures (212) are arranged in an alternate configuration;
a gate structure (264) surrounding the plurality of channel structures (206) and the plurality of dielectric fin structures (212); and
an isolation structure (282, 284) extending through the gate structure (264) and at least one of the plurality of channel structures (206), wherein the isolation structure (282, 284) is in contact with the at least one of the plurality of dielectric fin structures (212, 292)”.
Regarding independent claim 21, Yu’072 teaches, “A semiconductor device (fig. 1-34; ¶ [0001] - ¶ [0070]), comprising:
first and second channel structures (206, fig. 34A-D) on a substrate (202);
a plurality of dielectric fin structures (212, 292) comprising a stiff dielectric material (¶ [0027]) on the substrate (202),
wherein dielectric fin structure (212) is between the first and second channel structures (206);
a gate structure (264) on the first and second channel structures (206) and the dielectric fin structure (212, 292); and
an isolation structure (282, 284) extending through the gate structure (264) and the second channel structure (206),
wherein the isolation structure (282, 284) is in contact with the dielectric fin structure (212, 292)”.
Regarding claim 2, 11 and 22, Yu’072 further teaches, “wherein the dielectric fin structure (292) is on a top surface of an isolation layer (288, 284) and the stiff dielectric material (¶ [0028]) has a Young's modulus greater than about 75 GPa”.
Regarding claim 6, Yu’072 further teaches, “The semiconductor structure of claim 1, wherein a top surface of the dielectric fin structure (212) is below a top surface of the isolation structure (282, 284)”.
Regarding claim 7, 14 and 25, Yu’072 further teaches, “The semiconductor structure of claim 1, wherein a bottom surface of the dielectric fin structure (212, 292) is at a same level or above a top surface of the channel structure (206)”.
Regarding claim 8 and 15, Yu’072 further teaches, “The semiconductor structure of claim 1, wherein the isolation structure (284) extends into the substrate (202) and the dielectric fin structure (212) is surrounded by the isolation structure (284)”.
Regarding claim 9, Yu’072 further teaches, “The semiconductor structure of claim 1, wherein the isolation structure comprises a liner (288, 284C) in contact with the dielectric fin structure (292) and a dielectric fill (284B) on the liner”.
Regarding claim 13 and 24, Yu’072 further teaches, “wherein top surfaces of the gate structure and the isolation structure are coplanar (fig. 34).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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