DETAILED ACTION
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: AL2 (Specification ¶ [00181]).
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore elements, ‘zigzag line ..in a middle portion of the second stage transistor’, ‘second source electrode’, ‘second drain electrode’, ‘plurality of second gate insulating layer holes’ cited in claim 1 and 3, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
3. The display device of claim 1, wherein one side of each of the second source electrode and the second drain electrode is disposed in the plurality of second gate insulating layer holes, and another side of each of the second source electrode and the second drain electrode is disposed outside the plurality of second gate insulating layer holes.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 cites, ‘a first stage transistor’, ‘a second stage transistor’. But it is not understood from these limitations (first stage and second stage), which structural features are intended to be implied by the expression ‘stage’. For examination, no patentable weight will be given to ‘stage’.
Claims 2-19 are also rejected as they depend on the rejected claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-8 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita et al. (US 20080231560 A1, hereinafter Yamashita’560).
Regarding independent claim 1, Yamashita’560 teaches, “A display device (1, figs. 1-15; ¶ [0001] - ¶ [0285]), comprising:
a substrate (101, fig. 1) including a display area (102) and a non-display area adjacent to the display area (102), the display area (102) including a subpixel (P, fig. 2);
a driving transistor (121, fig. 2) and a light emitting diode (127) in the subpixel (110) on the substrate (101); and
a first stage transistor (600N, fig. 11) and a second stage transistor (600P) in the non-display area on the substrate,
wherein the second stage transistor (600P) includes a second active layer (616P), a second gate electrode (614GP), a second source electrode (618P) and a second drain electrode (620P),
wherein a gate insulating layer (under the gate in figs. 11-14) between the second active layer (616P) and the second source electrode (618P) and between the second active layer (616P),
wherein the second drain electrode (620P) exposes the second active layer and has a plurality of second gate insulating layer holes (622SP, 622DP), and
wherein the plurality of second gate insulating layer holes (622SP, 622DP) are disposed in a zigzag line (by connecting the first contact hole in the left column with the second contact hole in the right column further with the third contact hole in the left column and so forth) along a horizontal direction parallel to the second source electrode (618P) and the second drain electrode (620P) in a middle portion of the second stage transistor (600P)”.
Regarding claim 4, Yamashita’560 further teaches, “The display device of claim 1, wherein a first side of one of adjacent two of the plurality of second gate insulating layer holes (622SP, 622DP, fig. 11) corresponding to the second source electrode and a second side of the other of the adjacent two of the plurality of second gate insulating layer holes corresponding to the second source electrode are disposed to be coincide with each other along the horizontal direction”.
Regarding claim 5, Yamashita’560 further teaches, “The display device of claim 1, 5. The display device of claim 1, wherein a first portion of the plurality of second gate insulating layer holes (622SP, 622DP, fig. 11) corresponding to the second source electrode (618P) overlaps (in the ‘HORIZONTAL DIRECTION’ as shown in fig. 11) a first side of the second source electrode (618P) and is spaced apart from a second side of the second source electrode, and a second portion of the plurality of second gate insulating layer holes (622SP, 622DP) corresponding to the second source electrode (618P) is spaced apart from the first side of the second source electrode (618P) and overlaps the second side of the second source electrode (618P), and wherein a first portion of the plurality of second gate insulating layer holes (622SP, 622DP) corresponding to the second drain electrode (620P) overlaps a first side of the second drain electrode (620P) and is spaced apart from a second side of the second drain electrode (620P), and a second portion of the plurality of second gate insulating layer holes (622SP, 622DP) corresponding to the second drain electrode is spaced apart from the first side of the second drain electrode (620P) and overlaps the second side of the second drain electrode (620P)”.
Regarding claim 6, Yamashita’560 further teaches, “The display device of claim 1, 5. 6. The display device of claim 5, wherein the plurality of second gate insulating layer holes (622SP, 622DP, fig. 11) corresponding to the second source electrode (618P) in an upper portion of the second stage transistor overlap a first side of the second source electrode, and are spaced apart from a second side of the second source electrode (618P) to be disposed in a straight line along the horizontal direction, and wherein the plurality of second gate insulating layer holes (622SP, 622DP) corresponding to the second drain electrode (620P) in a lower portion of the second stage transistor overlap a first side of the second drain electrode (620P), and are spaced apart from a second side of the second drain electrode (620P) to be disposed in a straight line along the horizontal direction”.
Regarding claim 7, Yamashita’560 further teaches, “The display device of claim 1, wherein the second gate electrode (614G, fig. 11) includes a plurality of gate vertical parts and a plurality of gate horizontal parts connected to each other and symmetrically disposed with respect to a central line along a vertical direction (‘VERTICAL DIRECTION’) crossing the horizontal direction (‘HORIZONTAL DIRECTION’), wherein the second source electrode (618P) includes a source vertical part corresponding to the central line and a plurality of source horizontal parts extending from the source vertical part along the horizontal direction, and wherein the second drain electrode (620P) includes a drain vertical part at both sides of the central line and a plurality of drain horizontal parts extending from the drain vertical part along the horizontal direction”.
Regarding claim 8, Yamashita’560 further teaches, “The display device of claim 7, wherein the plurality of gate horizontal parts (614G, fig. 11), the plurality of source horizontal parts (620P) and the plurality of drain horizontal parts (618P) are disposed along the horizontal direction, and wherein the plurality of gate horizontal parts, the plurality of source horizontal parts and the plurality of drain horizontal parts are spaced apart from and parallel to each other along the vertical direction and are alternately disposed along the vertical direction”.
Regarding claim 13, Yamashita’560 further teaches, “The display device of claim 1, further comprising a gate driving unit (200/104WS, 105DS, fig. 1A) configured to generate a gate signal supplied to the display area (102) and having a plurality of blocks, and disposed in the non-display area, wherein the plurality of blocks include a clock signal block (CKAZ1 and CKAZ2), a high level voltage block (power lines connected to power potential Vc1 etc.), a stage circuit block (103) and a low level voltage block (ground lines Vcath etc.), and wherein a gate line (104WS, 105DS) transmitting the gate signal extends from the stage circuit block (103) to the display area (102) through the low level voltage block”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita’560.
Regarding claim 2, ‘The display device of claim 1, wherein the first stage transistor has a channel region of a linear shape, and the second stage transistor has a channel region of a bent shape’, Yamashita’560 teaches the first stage transistor (600N, fig. 11) has a channel region of a linear shape. Yamashita’560 may not be explicit on the provision of wherein the second stage transistor has a channel region of a bent shape. However, the applicant does not cite any evidence showing the criticality of this shape. The shape of the channel region is a matter of choice which a person skilled in the art would have found obvious absent persuasive evidence that the particular shape of the claimed limitation was significant, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yamashita’560 as applied to claim 1 as above, and further in view of Tai et al. (US 20210183895 A1, hereinafter Tai’895).
Regarding claim 3, Yamashita’560 teaches all the limitations described in claim 1.
But Yamashita’560 is silent upon the provision of wherein 3. The display device of claim 1, wherein one side of each of the second source electrode and the second drain electrode is disposed in the plurality of second gate insulating layer holes, and another side of each of the second source electrode and the second drain electrode is disposed outside the plurality of second gate insulating layer holes.
However, Tai’895 teaches a similar display device (fig. 1), wherein one side of each of the second source electrode (SD1, 120) and the second drain electrode (SD2) is disposed in the plurality of second gate insulating layer holes (131), and another side of each of the second source electrode (SD1, 120’) and the second drain electrode is disposed outside the plurality of second gate insulating layer holes.
Yamashita’560 and Tai’895 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamashita’560 with the features of Tai’895 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yamashita’560 and Tai’895 to arrange the S/D regions according to the teachings of Tai’895 with a motivation of reducing the chip size as described by Tai’895 in ¶ [0002] - ¶ [0005].
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita’560 as applied to claim 1 as above, and further in view of Tsuge (US 20190108789 A1, hereinafter Tsuge’789).
Regarding claim 9, Yamashita’560 teaches all the limitations described in claim 1.
But Yamashita’560 is silent upon the provision of wherein a ratio of a channel width with respect to a channel length of the first stage transistor is smaller than a ratio of a channel width with respect to a channel length of the second stage transistor.
However, Tsuge’789 teaches a similar display device, wherein a ratio of a channel width with respect to a channel length of the first stage transistor is smaller than a ratio of a channel width with respect to a channel length of the second stage transistor (claim 13).
Yamashita’560 and Tsuge’789 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamashita’560 with the features of Tsuge’789 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yamashita’560 and Tsuge’789 to form the channel length and width of the transistors according to the teachings of Tsuge’789 with a motivation of reducing uneven luminance of the display device. See Tsuge’789, ¶ [0007].
Regarding claim 10, Yamashita’560 modified with Tsuge’789 further teaches, “The display device of claim 9, wherein the first stage transistor (600N, fig. 11, Yamashita’560) includes a first active layer, a first gate electrode, a first source electrode and a first drain electrode, and wherein a gate insulating layer between the first active layer and the first source electrode and between the first active layer and the first drain electrode exposes the first active layer, and has a plurality of first gate insulating layer holes disposed in a straight line along a horizontal direction parallel to the first source electrode and the first drain electrode”.
Regarding claim 11, Yamashita’560 modified with Tsuge’789 further teaches, “The display device of claim 10, wherein one side of each of the first source electrode (618N, fig. 11, Yamashita’560) and the first drain electrode is disposed in the plurality of first gate insulating layer holes, and another side of each of the first source electrode and the first drain electrode is disposed outside the plurality of first gate insulating layer holes”.
Claim 12 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita’560 as applied to claim 1 as above, and further in view of Xu et al. (US 20180196556 A1, hereinafter Xu’556).
Regarding claim 12, Yamashita’560 teaches all the limitations described in claim 1.
But Yamashita’560 is silent upon the provision of wherein the display device of claim 1, further comprising a metal layer between the second active layer and the second source electrode and between the second active layer and the second drain electrode.
However, Xu’556 teaches a metal layer (7, fig. 9) between the second active layer (6) and the second source electrode (3) and between the second active layer (6) and the second drain electrode (4).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yamashita’560 and Xu’556 to include a metal layer between the S/D and active layer according to the teachings of Xu’556 ‘to reduce a contact resistance between the semiconductor layer 6 and the source electrode as well as the drain electrodes’. See Xu’556, ¶ [0076].
Claim 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita’560 as applied to claim 1 as above, and further in view of Jo et al. (US 20210202674 A1, hereinafter Jo’674).
Regarding claim 14, Yamashita’560 teaches all the limitations described in claim 1.
But Yamashita’560 is silent upon the provision of wherein the gate signal includes a scan signal and a sensing signal, and wherein the subpixel comprises: a switching transistor configured to be switched according to the scan signal, and connected to a data signal; a storage capacitor connected to the switching transistor; a driving transistor configured to be switched according to a voltage of a first capacitor electrode of the storage capacitor, and connected to a high level voltage; a reference transistor configured to be switched according to the sensing signal, and connected to the storage capacitor, the driving transistor and a reference signal; and the light emitting diode connected to the storage capacitor, the driving transistor, the reference transistor and a low level voltage.
However, Jo’674 teaches a similar device wherein the gate signal includes a scan signal and a sensing signal, and wherein the subpixel comprises: a switching transistor (ST, fig. 2) configured to be switched according to the scan signal, and connected to a data signal; a storage capacitor (Cst) connected to the switching transistor; a driving transistor (DT) configured to be switched according to a voltage of a first capacitor electrode of the storage capacitor, and connected to a high level voltage; a reference transistor configured to be switched according to the sensing signal, and connected to the storage capacitor, the driving transistor and a reference signal; and the light emitting diode (LD) connected to the storage capacitor, the driving transistor, the reference transistor and a low level voltage.
Yamashita’560 and Jo’674 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamashita’560 with the features of Jo’674 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yamashita’560 and Jo’674 to include driving transistor, switching transistor etc. according to the teachings of Jo’674 as these are essential and conventional elements of a display device.
Regarding claim 15, Yamashita’560 modified with Jo’674 further teaches, “The display device of claim 14, wherein at least one of the switching transistor, the driving transistor and the reference transistor includes an oxide semiconductor thin film transistor (¶ [0121], Jo’674)”.
Regarding claim 16, Yamashita’560 modified with Jo’674 further teaches, “wherein the stage circuit block generates (103) the scan signal and transmits the scan signal to the switching transistor (ST) through a gate line, and the stage circuit block (103) generates the sensing signal and transmits the sensing signal to the reference transistor through the gate line”.
Claim 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita’560 as applied to claim 1 as above, and further in view of Lee (KR 20160045392 A, hereinafter Lee’392) and Lee et al. (US 20200111858 A1, hereinafter Lee’858).
Regarding claim 17, Yamashita’560 teaches all the limitations described in claim 1.
But Yamashita’560 is silent upon the provision of wherein the display device of claim 1, further comprising: a light shielding layer in the subpixel on the substrate; a buffer layer between the light shielding layer and the driving transistor; an interlayer insulating layer between the driving transistor and the light emitting diode; an overcoat layer between the interlayer insulating layer and the light emitting diode; a bank layer on the overcoat layer; and a first encapsulating layer and a second encapsulating layer sequentially on the light emitting diode.
However, Lee’392 teaches a similar display device comprising: ((a light shielding layer in the subpixel on the substrate;)) a buffer layer (111) between the light shielding layer and the driving transistor; an interlayer insulating layer between the driving transistor and the light emitting diode (140); an overcoat layer (131) between the interlayer insulating layer and the light emitting diode; a bank layer (132) on the overcoat layer (131); and a first encapsulating layer (151) and a second encapsulating layer (153) sequentially on the light emitting diode (140).
Yamashita’560 and Lee’392 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yamashita’560 with the features of Lee’392 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Yamashita’560 and Lee’392 to include light emitting layer, light shielding layer, bank layer etc. according to the teachings of Lee’392 as these are essential and conventional elements of a display device.
Yamashita’560 modified with Lee’392 is silent upon the provision of wherein the display device of claim 1, further comprising: a light shielding layer in the subpixel on the substrate.
However, Lee’858 teaches a light shielding layer LS can be formed on the substrate SUB1 (e.g., see FIG. 7; ¶ [0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine Yamashita’560 modified with Lee’392 with Lee’858, because [t]he light shielding layer LS can be used to simply block external light or can be used as an electrode that facilitates a connection to other electrodes or lines and constitutes a capacitor, etc. (¶ [0045])
Regarding claim 18, Yamashita’560 modified with Lee’392 and Lee’858 further teaches, “The display device of claim 17, wherein the driving transistor includes: an active layer (121, fig. 2, Lee’392) on the buffer layer (111) corresponding to the light shielding layer (LS, Lee’858), a gate insulating layer and a gate electrode (122, Lee’392) sequentially on a central portion of the active layer, a source electrode (123) contacting a first end portion of the active layer and the light shielding layer, and a drain electrode (124) contacting a second end portion of the active layer”.
Regarding claim 19, Yamashita’560 modified with Lee’392 and Lee’858 further teaches, “The display device of claim 17, wherein the light emitting diode includes a first electrode (141) on the overcoat layer and connected to the source electrode, an emitting layer (142) on the first electrode and a second electrode on the emitting layer, and wherein the bank layer (132) covers an edge portion of the first electrode (141) and includes an opening exposing a central portion of the first electrode”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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