CTNF 18/444,359 CTNF 89965 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites limitations “an upper surface of the redistribution layer structure” twice (in lines 3-4 and lines 6-7). It is unclear whether the second recited “an upper surface of the redistribution layer structure” is intended to relate back to “an upper surface of the redistribution layer structure” recites in lines 3-4 or to set forth an additional upper surface of the redistribution layer structure. Claim 2 recites limitations “a second semiconductor stack structure” (line 2). However, claim 1 recites limitations “a second semiconductor stack structure” in line 6. It is unclear whether the second recited “an upper surface of the redistribution layer structure” (claim 2) is intended to relate back to “a second semiconductor stack structure” of claim 1 or to set forth an additional second semiconductor stack structure. Claim 4 recites limitations “a first active region” (line 3). However, claim 3 recites limitations “a first active region” in line 2. It is unclear whether the second recited “a first active region” (claim 4) is intended to relate back to “a first active region” of claim 3 or to set forth an additional first active region. Claim 6 recites limitations “a second active region” (line 3). However, claim 5 recites limitations “a second active region” in line 2. It is unclear whether the second recited “a second active region” (claim 6) is intended to relate back to “a second active region” of claim 5 or to set forth an additional second active region. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-2 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0415808 to Chava et al. (hereinafter Chava) in view of Wu et al. (US Patent No. 9,812,381, hereinafter Wu) . With respect to claim 1, Chava discloses a semiconductor package (300) (Chava, Fig. 4, ¶0023-¶0048), comprising: a redistribution layer structure (e.g., interconnect 122 of the substrate 102) (Chava, Fig. 4, ¶0024, ¶0045); a first semiconductor stack structure (e.g., 351/353) (Chava, Fig. 4, ¶0041, ¶0043-¶0045, ¶0049) on an upper surface (e.g., an upper surface of the substrate 102 including the interconnect 122) of the redistribution layer structure (122), wherein the first semiconductor stack structure comprises a first chiplet (e.g., 353) and a second chiplet (e.g., 351) disposed on the first chiplet (353); a second semiconductor stack structure (371/373) (Chava, Fig. 4, ¶0042-¶0046) on an upper surface (e.g., an upper surface of the substrate 102 including the interconnect 122) of the redistribution layer structure and side by side with the first semiconductor stack structure (351/353); a bridge die (e.g., bridge die 110 including bridge interconnect 112) (Chava, Fig. 4, ¶0027, ¶0043) forming an electrical connection between the first semiconductor stack structure (351/353) and the second semiconductor stack structure (371/373), the bridge die (110) being disposed above the first semiconductor stack structure (351/353) and the second semiconductor stack structure (371/373). Further, Chava does not specifically disclose a surface mount device (SMD) on an upper surface of at least one of the first semiconductor stack structure and the second semiconductor stack structure. However, Wu teaches forming a semiconductor package (Wu, Fig. 2G, Col. 5, lines 52-67; Col. 6, lines 1-15) comprising one or more bridge structures (600) to electrically connect the first die (100) and the second die (200), and the integrated passive device (530) formed on an upper surface of the interconnect (420), to provide die to die connections which allows the design for metallization layers for die connection to be more flexible, and to provide a compact package with improved integration density and increased yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava by forming the integrated passive device as a surface mount device (SMD) on an upper surface of the interconnect structure and adjacent to the bridge structure as taught by Wu to have the semiconductor package comprising: a surface mount device (SMD) on an upper surface of at least one of the first semiconductor stack structure and the second semiconductor stack structure, in order to provide a compact package including active and passive components and the external bridge structure for multi-die connection to improve integration density and to increase yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10). Regarding claim 2, Chava in view of Wu discloses the semiconductor package of claim 1. Further, Chava discloses the semiconductor package, wherein the first semiconductor stack structure (351/353) and a second semiconductor stack structure (371/373) exchange signals through the bridge die (110) (Chava, Fig. 4, ¶0027, ¶0043). With respect to claim 19, Chava discloses a method for manufacturing a semiconductor package (300) (Chava, Fig. 4, ¶0023-¶0048), the method comprising: mounting a first semiconductor stack structure (e.g., 351/353) (Chava, Fig. 4, ¶0041, ¶0043-¶0045, ¶0049) on a redistribution layer structure (e.g., interconnect 122 of the substrate 102) (Chava, Fig. 4, ¶0024, ¶0045), wherein the first semiconductor stack structure comprises a first chiplet (e.g., 353) and a second chiplet (e.g., 351) on the first chiplet (353); mounting a second semiconductor stack structure (371/373) (Chava, Fig. 4, ¶0042-¶0046), on the redistribution layer structure side by side with the first semiconductor stack structure (351/353); mounting a bridge die (e.g., bridge die 110 including bridge interconnect 112) (Chava, Fig. 4, ¶0027, ¶0043) on the first semiconductor stack structure (e.g., 351/353) and the second semiconductor stack structure (371/373), wherein the bridge die (110) is positioned above the first semiconductor stack structure (351/353) and the second semiconductor stack structure (371/373) and electrically connects the first semiconductor stack structure and the second semiconductor stack structure. Further, Chava does not specifically disclose mounting a surface mount device (SMD) on at least one of the first semiconductor stack structure and the second semiconductor stack structure. However, Wu teaches forming a semiconductor package (Wu, Fig. 2G, Col. 5, lines 52-67; Col. 6, lines 1-15) comprising one or more bridge structures (600) to electrically connect the first die (100) and the second die (200), and the integrated passive device (530) formed on an upper surface of the interconnect (420), to provide die to die connections which allows the design for metallization layers for die connection to be more flexible, and to provide a compact package with improved integration density and increased yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chava by forming the integrated passive device as a surface mount device (SMD) on an upper surface of the interconnect structure and adjacent to the bridge structure as taught by Wu to have the method comprising: mounting a surface mount device (SMD) on a at least one of the first semiconductor stack structure and the second semiconductor stack structure, in order to provide a compact package including active and passive components and the external bridge structure for multi-die connection to improve integration density and to increase yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10) . 07-21-aia AIA Claim s 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0415808 to Chava in view of Wu (US Patent No. 9,812,381) as applied to claim 1, and further in view of Park et al. (US 2022/0165722, hereinafter Park) . Regarding claims 3 and 4, Chava in view of Wu discloses the semiconductor package of claim 1. Further, Chava discloses the semiconductor package, wherein: the first chiplet (353) comprises a first region (e.g., a front side of the die 353) (Chava, Fig. 4, ¶0041-¶0043) positioned at a surface facing the second chiplet (351) (as claimed in claim 3), wherein the first chiplet (353) comprises a plurality of first through-silicon vias (e.g., TSV 453) (Chava, Fig. 4, ¶0041-¶0043) extending in a downward direction from a first region to a back side of the first chiplet (353) (as claimed in claim 4), but does not specifically disclose a first active region. However, Park teaches forming a stacked package (Park, Fig. 8, ¶0002, ¶0005, ¶0046-¶0047, ¶0055-¶0058) comprising a first chip (500) and a second chip (600) on the first chip, wherein the first chip (500) comprises a first active region (Park, Fig. 8, ¶0047) at a front surface of the first chip (500), and a front surface of the second chip (600) faces the first chip (500), to provide a semiconductor package with improved structural stability and electrical characteristics. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Wu by forming a first semiconductor chip including an active region arranged at front surface of the first semiconductor chip as taught by Park to have the semiconductor package, wherein the first chiplet comprises a first active region, in order to provide a stacked semiconductor package with improved structural stability and electrical characteristics (Park, ¶0002, ¶0005, ¶0047). Regarding claims 5 and 6, Chava in view of Wu discloses the semiconductor package of claim 1. Further, Chava discloses the semiconductor package, wherein the second chiplet (351) comprises a second region (e.g., a front side of the die 351) (Chava, Fig. 4, ¶0041-¶0043) positioned at surface facing the first chiplet (353) (as claimed in claim 5); wherein the second chiplet (351) comprises a plurality of second through-silicon vias (e.g., TSV 451) (Chava, Fig. 4, ¶0041-¶0043) extending in an upward direction from a second region to a back side of the second chiplet (351) (as claimed in claim 6), but does not specifically disclose a second active region. However, Park teaches forming a stacked package (Park, Fig. 8, ¶0002, ¶0005, ¶0046-¶0047, ¶0055-¶0058) comprising a first chip (500) and a second chip (600) on the first chip, wherein the first chip (500) comprises a first active region (Park, Fig. 8, ¶0047) at a front surface of the first chip (500), and a front surface of the second chip (600) faces the first chip (500), to provide a semiconductor package with improved structural stability and electrical characteristics. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Wu by forming a semiconductor chip including an active region arranged at front surface of the semiconductor chip as taught by Park to have the semiconductor package, wherein the second chiplet comprises a second active region, in order to provide a stacked semiconductor package with improved structural stability and electrical characteristics (Park, ¶0002, ¶0005, ¶0047). Regarding claim 7, Chava in view of Wu and Park discloses the semiconductor package of claim 6. Further, Chava discloses the semiconductor package, wherein each of the plurality of second through-silicon vias (TSV 451) is electrically connected to one (e.g., bridge interconnect 112 of the bridge die 110) (Chava, Fig. 4, ¶0043) of the bridge die or the surface mount device. Regarding claim 8, Chava in view of Wu discloses the semiconductor package of claim 1. Further, Chava does not specifically disclose the first chiplet has a first footprint and the second chiplet has a second footprint, and the first footprint is within the second footprint. However, Park teaches forming a stacked package (Park, Fig. 8, ¶0002, ¶0005, ¶0046-¶0047, ¶0055-¶0058) comprising a first chip (500) and a second chip (600) on the first chip, wherein the first chip (500) (Park, Fig. 8, ¶0055) has a side surface recessed from a side surface of the second chip (600), and a molding layer (710) (Park, Fig. 8, ¶0053) cover the side surface of the first chip (500) to protect the first semiconductor chip (500). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Wu by forming a first semiconductor chip including side surfaces recessed from side surfaces of the second semiconductor chip as taught by Park to have the semiconductor package, wherein the first chiplet has a first footprint and the second chiplet has a second footprint, and the first footprint is within the second footprint, in order to provide a stacked semiconductor package with improved structural stability and electrical characteristics (Park, ¶0002, ¶0005, ¶0047) . 07-21-aia AIA Claim s 9 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0415808 to Chava in view of Park (US 2022/0165722), Wu (US Patent No. 9,812,381), and Elsherbini et al. (US 2020/03664600, hereinafter Elsherbini) . With respect to claim 9, Chava discloses a semiconductor package (300) (Chava, Fig. 4, ¶0023-¶0048), comprising: a redistribution layer structure (e.g., interconnect 122 of the substrate 102) (Chava, Fig. 4, ¶0024, ¶0045); a first semiconductor stack structure (e.g., 351/353) (Chava, Fig. 4, ¶0041, ¶0043-¶0045, ¶0049) on the redistribution layer structure (e.g., an upper surface of the substrate 102 including the interconnect 122), wherein the first semiconductor stack structure comprises, a first chiplet (e.g., 353), a second chiplet (e.g., 351) on the first chiplet (353) such that the first chiplet (353) is disposed between the redistribution layer structure (122) and the second chiplet (351), and a first interconnection structure (354) between the first chiplet (353) and the second chiplet (351); a second semiconductor stack structure (371/373) (Chava, Fig. 4, ¶0042-¶0046) disposed on the redistribution layer structure (e.g., an upper surface of the substrate 102 including the interconnect 122) and side by side with the first semiconductor stack structure (351/353); a bridge die (e.g., bridge die 110 including bridge interconnect 112) (Chava, Fig. 4, ¶0027, ¶0043) configured to electrically connect the first semiconductor stack structure (351/353) and the second semiconductor stack structure (371/373), the bridge die (110) being disposed above the first semiconductor stack structure (351/353) and the second semiconductor stack structure (371/373). Further, Chava does not specifically disclose (1) a first molding material molding a side surface of the first chiplet, a second chiplet on the first molding material; and a second molding material covering the first semiconductor stack structure, the second semiconductor stack structure, on the redistribution layer structure; (2) a surface mount device (SMD) disposed above at least one of the first semiconductor stack structure and the second semiconductor stack structure; (3) a second molding material covering the bridge die, and the surface mount device. Regarding (1), Park teaches forming a stacked package (Park, Fig. 8, ¶0002, ¶0005, ¶0046-¶0047, ¶0055-¶0058) comprising a first chip (500) and a second chip (600) on the first chip, wherein the first chip (500) (Park, Fig. 8, ¶0055) has a side surface recessed from a side surface of the second chip (600), and a first molding layer (710) (Park, Fig. 8, ¶0053) cover the side surface of the first chip (500) such that the second chip (600) is disposed on the first molding material (710), and a second molding material (800) (Park, Fig. 8, ¶0064) covering the first semiconductor stack structure (CS1), the second semiconductor stack structure (CS2), on the redistribution layer structure (200/210) (Park, Fig. 8, ¶0025). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Wu by forming a first semiconductor chip including side surfaces recessed from side surfaces of the second semiconductor chip as taught by Park to have the semiconductor package, wherein the first chiplet has a first footprint and the second chiplet has a second footprint, and the first footprint is within the second footprint, in order to provide a stacked semiconductor package with improved structural stability and electrical characteristics (Park, ¶0002, ¶0005, ¶0047). Regarding (2), Wu teaches forming a semiconductor package (Wu, Fig. 2G, Col. 5, lines 52-67; Col. 6, lines 1-15) comprising one or more bridge structures (600) to electrically connect the first die (100) and the second die (200), and the integrated passive device (530) formed on an upper surface of the interconnect (420), to provide die to die connections which allows the design for metallization layers for die connection to be more flexible, and to provide a compact package with improved integration density and increased yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava by forming the integrated passive device as a surface mount device (SMD) on an upper surface of the interconnect structure and adjacent to the bridge structure as taught by Wu to have the semiconductor package comprising: a surface mount device (SMD) disposed above at least one of the first semiconductor stack structure and the second semiconductor stack structure, in order to provide a compact package including active and passive components and the external bridge structure for multi-die connection to improve integration density and to increase yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10). Regarding (3), Elsherbini teaches forming a package (Elsherbini, Figs. 1, 8, ¶0040-¶0047, ¶0056, ¶0074) including a plurality of stacked dies (114), wherein a single die (e.g., 114-11) is a bridge to other underlying dies (e.g., 114-9 and 114-10), and a molding material (127) extending around and above the plurality of dies (114), wherein the mold material has a coefficient of thermal expansion to mitigate/minimize the stress between the dies (114) and the package substrate (102). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Park/Wu by forming a molding material extending around and above the plurality of stacked dies including a bridge die as taught by Elsherbini to have the semiconductor package, wherein the plurality of stacked dies includes passive device to have the semiconductor package comprising: a second molding material covering the bridge die, and the surface mount device, in order to efficiently mitigate/minimize the stress between the dies and the package substrate (Elsherbini, ¶0056, ¶0074). Regarding claim 13, Chava in view of Park, Wu, and Elsherbini discloses the semiconductor package of claim 9. Further, Chava does not specifically disclose the surface mount device comprises a capacitor structure. However, Wu teaches forming a semiconductor package (Wu, Fig. 2G, Col. 2, lines 43-48; Col. 5, lines 52-67; Col. 6, lines 1-15) comprising one or more bridge structures (600) to electrically connect the first die (100) and the second die (200), and the integrated passive device (530) formed on an upper surface of the interconnect (420), wherein the integrated passive device (530) comprises a capacitor structure, to provide die to die connections which allows the design for metallization layers for die connection to be more flexible, and to provide a compact package with improved integration density and increased yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Park/Wu/Elsherbini by forming the integrated passive device as a surface mount device (SMD) as taught by Wu to have the semiconductor package, wherein the surface mount device comprises a capacitor structure, in order to provide a compact package including active and passive components and the external bridge structure for multi-die connection to improve integration density and to increase yield of the package (Wu, Col. 15-25; Col. 7, lines 56-67; Col. 8, lines 1-10). Regarding claim 14, Chava in view of Park, Wu, and Elsherbini discloses the semiconductor package of claim 9. Further, Chava discloses the semiconductor package, further comprising a second interconnection structure (125/127) (Chava, Fig. 4, ¶0027, ¶0041- ¶0046) between the first semiconductor stack structure (351/353), the second semiconductor stack structure (371/373), and the bridge die (110) . 07-21-aia AIA Claim s 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0415808 to Chava in view of Park (US 2022/0165722), Wu (US Patent No. 9,812,381), and Elsherbini (US 2020/03664600), as applied to claim 9, and further in view of Malladi et al. (US 2019/0050325, hereinafter Malladi) . Regarding claim 10, Chava in view of Park, Wu, and Elsherbini discloses the semiconductor package of claim 9. Further, Chava discloses that the first semiconductor stack structure (351/353) (Chava, Fig. 4, ¶0041, ¶0043-¶0045, ¶0049) comprises a chiplet including a processor, a memory, and a passive device, but does not specifically disclose that the first chiplet comprises a central processing unit (CPU) or a graphic processing unit (GPU). However, Malladi teaches forming a semiconductor module comprising a memory structure (Malladi, Figs. 2, 6, ¶0001-¶0002, ¶0019-¶0025, ¶0041-¶0042) on a logic die (105) disposed beneath the memory module (e.g., high band width memory (HBM) stack), wherein the logic die (105) is connected to the host (115) comprising a central processing unit (CPU) or a graphic processing unit (GPU) and includes SRAM and HBM controller (Malladi, Figs. 2, 6, ¶0041-¶0042), to provide a semiconductor circuit with increased performance and reduced energy consumption. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Park/Wu/Elsherbini by forming a semiconductor package including a memory stack on the logic device as taught by Malladi to have the semiconductor package, wherein the first chiplet comprises a central processing unit (CPU) or a graphic processing unit (GPU), in order to provide a semiconductor circuit with increased performance and reduced energy consumption (Malladi, ¶0001-¶0002, ¶0019-¶0025). Regarding claim 11, Chava in view of Park, Wu, and Elsherbini discloses the semiconductor package of claim 9. Further, Chava discloses that the first semiconductor stack structure (351/353) (Chava, Fig. 4, ¶0041, ¶0043-¶0045, ¶0049) comprises a chiplet including a processor, a memory, and a passive device, but does not specifically disclose that the second chiplet comprises an SRAM. However, Malladi teaches forming a semiconductor module comprising a memory structure (Malladi, Figs. 2, 6, ¶0001-¶0002, ¶0019-¶0025, ¶0041-¶0042) on a logic die (105) disposed beneath the memory module (e.g., high band width memory (HBM) stack), wherein the logic die (105) is connected to the host (115) comprising a central processing unit (CPU) or a graphic processing unit (GPU) and includes SRAM and HBM controller (Malladi, Figs. 2, 6, ¶0041-¶0042), wherein the SAM controller interface with SRAM memory, to provide a semiconductor circuit with increased performance and reduced energy consumption. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Park/Wu/Elsherbini by forming a semiconductor package including a memory stack on the logic device as taught by Malladi, wherein the memory includes SRAM memory to have the semiconductor package, wherein the second chiplet comprises an SRAM, in order to provide a semiconductor circuit with increased performance and reduced energy consumption (Malladi, ¶0001-¶0002, ¶0019-¶0025). Regarding claim 12, Chava in view of Park, Wu, and Elsherbini discloses the semiconductor package of claim 9. Further, Chava discloses that the first semiconductor stack structure (351/353) (Chava, Fig. 4, ¶0041, ¶0043-¶0045, ¶0049) comprises a chiplet including a processor, a memory, and a passive device, but does not specifically disclose that the second chiplet comprises a high-bandwidth memory (HBM). However, Malladi teaches forming a semiconductor module comprising a memory structure (Malladi, Figs. 2, 6, ¶0001-¶0002, ¶0019-¶0025, ¶0041-¶0042) on a logic die (105) disposed beneath the memory module (e.g., high band width memory (HBM) stack), wherein the logic die (105) is connected to the host (115) comprising a central processing unit (CPU) or a graphic processing unit (GPU) and includes HBM controller (Malladi, Figs. 2, 6, ¶0041-¶0042), to provide a semiconductor circuit with increased performance and reduced energy consumption. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Park/Wu/Elsherbini by forming a semiconductor package including a memory stack on the logic device as taught by Malladi, wherein the memory includes HBM memory to have the semiconductor package, wherein the second chiplet comprises a high-bandwidth memory (HBM), in order to provide a semiconductor circuit with increased performance and reduced energy consumption (Malladi, ¶0001-¶0002, ¶0019-¶0025) . 07-21-aia AIA Claim s 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0415808 to Chava in view of Park (US 2022/0165722), Wu (US Patent No. 9,812,381), and Elsherbini (US 2020/03664600), as applied to claim 14, and further in view of Chen (US 2023/0335519) . Regarding claim 15, Chava in view of Park, Wu, and Elsherbini discloses the semiconductor package of claim 14. Further, Chava discloses the semiconductor package, wherein the second interconnection structure (125/127, solder interconnects or bumps) (Chava, Fig. 4, ¶0027, ¶0052) comprises a bump, but does not specifically disclose a micro-bump. However, Chen teaches forming a conductive connector (128) (Chen, Figs. 6-7, ¶0009, ¶0038-¶0042) including a micro-bump between the semiconductor chip (50B) and the underlying interconnect structure (121) for solder bonding, to provide a semiconductor package having improved device performance and reduced costs. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Park/Wu/Elsherbini by forming a semiconductor package by using solder bonding as taught by Chen to have the semiconductor package, wherein the second interconnection structure comprises a micro-bump, in order to provide a semiconductor package having improved device performance and reduced costs (Chen, ¶0009, ¶0038-¶0042). Regarding claims 16-18, Chava in view of Park, Wu, and Elsherbini discloses the semiconductor package of claim 14. Further, Chava does not specifically disclose that the second interconnection structure comprises: a first silicon insulation layer and a plurality of first bonding pads on an upper surface of the second chiplet and on an upper surface of the second semiconductor stack structure; and a second silicon insulation layer and a plurality of second bonding pads on a bottom surface of the bridge die (as claimed in claim 16), wherein each bonding pad of the plurality of first bonding pads is directly bonded to each second bonding pad of the plurality of second bonding pads (as claimed in claim 17); wherein the first silicon insulation layer is directly bonded to the second silicon insulation layer (as claimed in claim 18). However, Chen teaches forming a semiconductor package using mixed bond types, wherein the semiconductor chip (50A) (Chen, Figs. 6-7, ¶0009, ¶0028-¶0037) is bonded to the interface die (111) by direct bonding such that a first silicon insulation layer (120) (Chen, Figs. 6-7, ¶0031) and a plurality of first bonding pads (122) are formed on an upper surface of the die (111), and a second silicon insulation layer (68) (Chen, Figs. 6-7, ¶0017, ¶0035) and a plurality of second bonding pads (66) are formed on a bottom surface of the die (50A), wherein each bonding pad (122) of the plurality of first bonding pads is directly bonded to each second bonding pad (66) of the plurality of second bonding pads, and wherein the first silicon insulation layer (120) (Chen, Figs. 6-7, ¶0031, ¶0034-¶0037) is directly bonded (e.g., oxide-to-oxide bond) to the second silicon insulation layer (68), to provide high density die-to-die interconnections having smaller pitch connections and reduced defects to improve device performance. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor package of Chava/Park/Wu/Elsherbini by forming a semiconductor package using direct bonding between the dies as taught by Chen to have the semiconductor package, wherein the second interconnection structure comprises: a first silicon insulation layer and a plurality of first bonding pads on an upper surface of the second chiplet and on an upper surface of the second semiconductor stack structure; and a second silicon insulation layer and a plurality of second bonding pads on a bottom surface of the bridge die (as claimed in claim 16), wherein each bonding pad of the plurality of first bonding pads is directly bonded to each second bonding pad of the plurality of second bonding pads (as claimed in claim 17); wherein the first silicon insulation layer is directly bonded to the second silicon insulation layer (as claimed in claim 18), in order to provide high density die-to-die interconnections having smaller pitch connections and reduced defects to improve device performance (Chen, ¶0009, ¶0034-¶0037) . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0415808 to Chava in view of Wu (US Patent No. 9,812,381) as applied to claim 19, and further in view of Chen (US 2023/0335519) . Regarding claim 20, Chava in view of Wu discloses the method of claim 19. Further, Chava does not specifically disclose the method, wherein: the bridge die is mounted on the first semiconductor stack structure and on the second semiconductor stack structure by hybrid bonding. However, Chen teaches forming a semiconductor package, wherein the circuit die (50A) is bonded to backside interconnect by hybrid bonding (Chen, Figs. 6-7, ¶0009, ¶0033-¶0037) including oxide-to-oxide bond and metal-to-metal bonding, to provide a semiconductor package having improved device performance. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Chava/Wu by forming a semiconductor package by using oxide-to-oxide bond and metal-to-metal bond as taught by Chen to have the method, wherein: the bridge die is mounted on the first semiconductor stack structure and on the second semiconductor stack structure by hybrid bonding, in order to provide a high density die-to-die interconnections having smaller pitch connections and reduced defects to improve device performance (Chen, ¶0009, ¶0034-¶0037). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891 Application/Control Number: 18/444,359 Page 2 Art Unit: 2891 Application/Control Number: 18/444,359 Page 3 Art Unit: 2891 Application/Control Number: 18/444,359 Page 4 Art Unit: 2891 Application/Control Number: 18/444,359 Page 5 Art Unit: 2891 Application/Control Number: 18/444,359 Page 6 Art Unit: 2891 Application/Control Number: 18/444,359 Page 7 Art Unit: 2891 Application/Control Number: 18/444,359 Page 8 Art Unit: 2891 Application/Control Number: 18/444,359 Page 9 Art Unit: 2891 Application/Control Number: 18/444,359 Page 10 Art Unit: 2891 Application/Control Number: 18/444,359 Page 11 Art Unit: 2891 Application/Control Number: 18/444,359 Page 12 Art Unit: 2891 Application/Control Number: 18/444,359 Page 13 Art Unit: 2891 Application/Control Number: 18/444,359 Page 14 Art Unit: 2891 Application/Control Number: 18/444,359 Page 15 Art Unit: 2891 Application/Control Number: 18/444,359 Page 16 Art Unit: 2891 Application/Control Number: 18/444,359 Page 17 Art Unit: 2891 Application/Control Number: 18/444,359 Page 18 Art Unit: 2891
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