Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 16, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of Invention II (claims 11-20) in the reply filed on 06/15/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-13, 15-16, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kohji et al. (Pub. No.: US 2015/0004777 A1).
Regarding Claim 11, Kohji et al. discloses a manufacturing method of a semiconductor device, comprising:
forming a stacking structure that includes a plurality of sacrificial insulating layers
and a plurality of insulating layers alternately stacked with each other (Par. 0048-0052; Figs. 3-14D - plurality of sacrificial insulating layers 122 and plurality of insulating layers 121);
forming a plurality of preliminary channel structures that penetrate the stacking
structure and that include a plurality of preliminary channel layers, wherein each of the
plurality of preliminary channel layers has an amorphous structure (Par. 0058-0062; Figs. 12-14D – preliminary channel structure 140P comprising amorphous channel layer 142a);
forming a plurality of channel layers that have a single crystal structure or a quasi-
single crystal structure and have the same crystal orientation, by performing a heat treatment process that crystallizes the plurality of preliminary channel layers of the plurality of preliminary channel structures (Par. 0063-0067; Figs. 14A-14D – channel layer 142 has a single crystal structure); and
forming a plurality of gate electrodes by replacing the plurality of sacrificial
insulating layers with the plurality of gate electrodes (Par. 0063-0067; Figs. 23-27 – gate electrode 123).
Regarding Claim 12, Kohji et al., as applied to claim 11, discloses the manufacturing method, wherein the plurality of preliminary channel structures include a first preliminary channel structure that includes a first preliminary channel layer, and a plurality of second preliminary channel structures adjacent to the first preliminary channel structure and that include a plurality of second preliminary channel layers (Fig. 1), and
wherein forming the plurality of channel layers includes respectively crystallizing
the first preliminary channel layer and the plurality of second preliminary channel layers
into a first channel layer and a plurality of second channel layers that have a same crystal
orientation (Fig. 1).
Regarding Claim 13, Kohji et al., as applied to claim 11, discloses the manufacturing method, further comprising:
positioning a metal-containing layer that includes a metal and has a single crystal
structure or a quasi-single crystal structure on the plurality of preliminary channel structures, between forming the plurality of preliminary channel structures and forming
the plurality of channel layers (Par. 0062-0067; Figs. 14A-14D – amorphous silicon layer for crystallization 210a is crystallized by diffusing metal of the metal catalytic layer 230 into it through an annealing process; this layer 210a post-annealing could be considered as the metal containing layer that includes a metal and has a single crystal structure), and
removing the metal-containing layer from the stacking structure between forming
of the plurality of channel layers and forming of the plurality of gate electrodes (Par. 0062-0067; Figs. 14A-14D),
wherein, forming the plurality of channel layers includes crystallizing the plurality
of preliminary channel layers by a metal-induced crystallization or a metal-induced lateral
crystallization (Par. 0062-0067; Figs. 14A-14D – plurality of channel layers 142)
Regarding Claim 15, Kohji et al., as applied to claim 13, discloses the manufacturing method, wherein the metal-containing layer includes a metal-semiconductor compound in which a metal and a semiconductor material are chemically bonded (Par. 0062-0067; Figs. 14A-14D; also see Par. 0087-0092; Figs. 15A-17D)
Regarding Claim 16, Kohji et al., as applied to claim 15, discloses the manufacturing method, wherein the metal-containing layer includes a metal silicide (Par. 0062-0067; Figs. 14A-14D; also see Par. 0087-0092; Figs. 15A-17D)
Regarding Claim 18, Kohji et al., as applied to claim 13, discloses the manufacturing method, further comprising forming an amorphous semiconductor layer on the stacking structure between forming the plurality of preliminary channel structures and positioning of the metal-containing layer (Par. 0059-0067; Figs. 14A-14D – amorphous semiconductor layer 144a (amorphous channel pad patterns)),
wherein positioning the metal-containing layer includes positioning the metal-containing layer on the amorphous semiconductor layer (Par. 0059-0067; Figs. 14A-14D – in light of the rejection of claim 13)
Regarding Claim 20, Kohji et al., as applied to claim 13, discloses the manufacturing method, wherein removing the metal- containing layer is performed by at least one of chemical mechanical polishing, dry etching, or wet etching (Par. 0059-0067; Figs. 14A-14D – chemical mechanical polishing)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17 and 19 are rejected under 35 U.S.C. 103 as obvious over Kohji et al. (Pub. No.: US 2015/0004777 A1), as applied to claims 13 and 18, respectively.
Regarding Claim 17, Kohji et al., as applied to claim 13, does not explicitly disclose the manufacturing method, wherein the metal-containing layer has a thickness of 10 nm to 100 nm. However, it is clear from the teachings of Kohji et al. is that the thickness of the metal containing layer has to be such that it efficiently drives the crystallization process of the amorphous preliminary channel layers. Also, it should not be unnecessarily thick as it would not be cost effective. Kohji et al. discloses the claimed invention except for the manufacturing method, wherein the metal-containing layer has a thickness of 10 nm to 100 nm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the manufacturing method, wherein the metal-containing layer has a thickness of 10 nm to 100 nm., since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 19, Kohji et al., as applied to claim 18, does not explicitly disclose the manufacturing method, wherein the amorphous semiconductor layer has a thickness of 20 nm to 100 nm. However, it is clear from the teachings of Kohji et al. is that the thickness of the amorphous semiconductor layer has to be such that it acts as an effective pad. Also, it should not be unnecessarily thick as it would not be cost effective. Kohji et al. discloses the claimed invention except for the manufacturing method, wherein the amorphous semiconductor layer has a thickness of 20 nm to 100 nm. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the manufacturing method, wherein the amorphous semiconductor layer has a thickness of 20 nm to 100 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pachamuthu et al. (Pub. No.: US 9478495 B1) – This prior art teaches a manufacturing method of a semiconductor device, comprising most of the limitations recited by independent claim 11
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07/08/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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