DETAILED ACTION
The RCE filed April 29, 2026 has been entered. Claims 1-9 are pending. Claim 1 is independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by M Siddiqui et al. (US 12,243,585).
Regarding independent claim 1, M Siddiqui et al. disclose a memory device (see e.g., FIGS. 1B and FIG. 2, and EXMINER’S MARKUP below), comprising:
a memory array (FIG. 1B: 108);
an input/output (IO) circuitry (see FIG. 1B), configured to access the memory array, wherein the IO circuit comprises:
a write driver (152-0/152-0B), configured to receive input data to drive bit lines (DL/DL0) of the memory array; and
a negative voltage provider (FIG. 2: 210 and 126), configured to generate to generate a negative voltage (FIGS. 1B and 2: VSS_ASSIST) to the write driver (FIG. 1B: 152, i.e., VSS_ASSIST through 150 to 152); and
a control circuit (see FIGS. 1B and 2), comprising:
a negative-bit-line (NBL) timing control circuit, configured to generate an NBL enable signal to selectively enable (FIG. 2: GWA_CLK after 212) the negative voltage provider (210 and 126);
wherein the memory device is supplied by a first supply voltage (VDDP) and a second supply voltage (VDD_M), and a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage (see FIG. 2: 212); and the negative voltage provider and the NBL timing control circuit are supplied by the second supply voltage (VDD_M).
wherein the negative voltage provider (FIG. 2: 210 and 126) comprises at least one inverter supplied by the second supply voltage and at least one transistor, and the NB enable signal passes through the at least one inverter to control the at least one transistor to selectively generate the negative voltage (see FIG. 2).
Regarding claim 4, which depends from claim 1, M Siddiqui et al. disclose the control circuit is supplied by both the first supply voltage and the second supply voltage (see e.g., FIGS. 1B and 2).
Regarding claim 9, which depends from claim 1, M Siddiqui et al. disclose the memory device is a dual-rail static random access memory (SRAM) circuitry (see FIG. 1B: 108).
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Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 5-8 are rejected under AIA 35 U.S.C. 103 as being unpatentable over M Siddiqui et al. (US 12,243,585).
Regarding claim 2, M Siddiqui et al. teach the limitations of claim 1.
M Siddiqui et al. do not explicitly disclose when the memory array operates in a normal mode, the first supply voltage has a normal voltage level; and when the memory operates in a power saving mode, the first supply voltage has a low voltage level different from the normal voltage level; and the second supply voltage has the same voltage level regardless whether the memory device operates in the normal mode or the power saving mode.
However, the claimed limitations of a normal operation mode and a power saving mode having different supply powers is a well-known technology in a memory device and operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in power saving because these conventional technology are well established in the art of the memory devices.
Regarding claim 3, M Siddiqui et al. teach the limitations of claim 1.
M Siddiqui et al. do not explicitly disclose the IO circuitry further comprises a sense amplifier, an input latch and an output driver, and at least one of the write driver, the sense amplifier, the input larch and the output driver is supplied by the first supply voltage.
However, the claimed limitations of a SA, input data latch and an output driver in a low power domain is a well-known technology in a memory device and operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory power saving peripheral circuitry because these conventional technology are well established in the art of the memory devices.
Regarding claim 5, M Siddiqui et al. teach the limitations of claim 4.
M Siddiqui et al. further teach a pre-driver and a post-driver, the pre-driver is supplied by the second supply voltage, and the post-driver is supplied by the first supply voltage (see e.g., FIGS. 1B and 2).
Further, pre and post driver circuitry having multi-power is a well-known technology in a memory device and operations.
For support, of the above asserted facts, see for example, Cheng et al. (US 2019/0115056), FIG. 4, i.e., write driver circuit comprising 1130 in high-voltage VDDM power domain (claimed the second power voltage) and 1132 in low-voltage VDD power domain (claimed the first power voltage).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Cheng et al. to the teaching of M Siddiqui et al. such that a memory, as taught by M Siddiqui et al., utilizes dual-rail driver circuitry in a multi-power domain, as taught by Cheng et al., for the purpose of enhancing memory write operation, and further these conventional technology are well established in the art of the memory devices.
Regarding claims 6-8, M Siddiqui et al. teach the limitations of claim 5.
M Siddiqui et al. further teach the pre-driver receives a clock signal to generate a processed signal, and the post-driver receives the processed signal to generate an output clock signal serving as the global IO signal to the IO circuitry; a signal generator supplied by the first supply voltage, configured to generate a first clock signal; and a level shift circuit, configured to receive the first clock signal to generate the clock signal, wherein a voltage level of the clock signal is higher than a voltage level of the first clock signal; and each of the pre-driver and the post-driver comprises an inverter (FIGS. 2, 4-5 and 7, and accompanying disclosure).
Response to Arguments
Applicant’s RCE filed 04/29/2025, with respect to the rejection(s) of claims 1-9 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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