DETAILED ACTION
The Amendment filed October 28, 2025 has been entered. Claims 1-9 are pending. Claim 1 is independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu (US 2010/0182865).
Regarding independent claim 1, the claimed limitations of negative bit line voltage in write operations of memory is a well-known technology for a type of memory (e.g., SRAM) for its purpose. For support, see for example, Wu discloses a memory device, comprising:
a memory array (FIG. 3: 20);
an input/output (IO) circuitry (see FIG. 3), configured to access the memory array, wherein the IO circuit comprises:
a write driver (transistors coupled to DL/DLB, and para. 0022: During a write operation of SRAM cell; and para. 0026: … Such behavior of the negative voltage fits the need for write operations of SRAM cell), configured to receive input data to drive bit lines (DL/DLB) of the memory array; and
a negative voltage provider (26), configured to generate to generate a negative voltage (voltage at 24) to the write driver (transistors coupled to DL/DLB); and
a control circuit (see FIG. 3), comprising:
a negative-bit-line (NBL) timing control circuit, configured to generate an NBL enable signal to selectively enable (SC1/SC2 through IN1/2 to INV1/2, i.e., enabling NBL by input IN1/IN2 though output INV1/2) the negative voltage provider;
wherein the memory device is supplied by a first supply voltage (VDD) and a second supply voltage (High Voltage Source 38), and a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage (para. 0028: … the high supply voltage HV … higher than voltage VDD); and the negative voltage provider (26) and the NBL timing control circuit (from SC1/SC2, through IN1/2, to INV1/2, i.e., enabling NBL by input IN1/IN2 though output INV1/2) are supplied by the second supply voltage (see 38 and 26).
Regarding claim 4, which depends from claim 1, Wu discloses the control circuit is supplied by both the first supply voltage and the second supply voltage (FIG. 3: VDD and 38 for 26).
Regarding claim 9, which depends from claim 1, Wu discloses the memory device is a dual-rail static random access memory (SRAM) circuitry (see FIG. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 5 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu (US 2010/0182865).
Regarding claim 2, Wu teaches the limitations of claim 1.
Wu do not explicitly disclose when the memory array operates in a normal mode, the first supply voltage has a normal voltage level; and when the memory operates in a power saving mode, the first supply voltage has a low voltage level different from the normal voltage level; and the second supply voltage has the same voltage level regardless whether the memory device operates in the normal mode or the power saving mode.
However, the claimed limitations of a normal operation mode and a power saving mode having different supply powers is a well-known technology in a memory device and operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in power saving because these conventional technology are well established in the art of the memory devices.
Regarding claim 3, Wu teaches the limitations of claim 1.
Wu do not explicitly disclose the IO circuitry further comprises a sense amplifier, an input latch and an output driver, and at least one of the write driver, the sense amplifier, the input larch and the output driver is supplied by the first supply voltage.
However, the claimed limitations of a SA, input data latch and an output driver in a low power domain is a well-known technology in a memory device and operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory power saving peripheral circuitry because these conventional technology are well established in the art of the memory devices.
Regarding claim 5, Wu teaches the limitations of claim 4.
Wu further teaches a pre-driver (FIG. 3: INV1) and a post-driver (INV2), the pre-driver is supplied by the second supply voltage, and the post-driver is supplied by the first supply voltage (see FIG. 3).
Wu’s pre and post driver does not explicitly disclose the second and first supply voltages.
However, the claimed limitations of driver circuitry having multi-power is a well-known technology in a memory device and operations.
For support, of the above asserted facts, see for example, Cheng et al. (US 2019/0115056), FIG. 4, i.e., write driver circuit comprising 1130 in high-voltage VDDM power domain (claimed the second power voltage) and 1132 in low-voltage VDD power domain (claimed the first power voltage).
Wu and Cheng are analogous art because they both are directed to dual-rail memory (e.g., SRAM) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu with the specified features of Cheng because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Cheng et al. to the teaching of Wu such that a memory, as taught by Wu, utilizes dual-rail driver circuitry in a multi-power domain, as taught by Cheng et al., for the purpose of enhancing memory write operation, and further these conventional technology are well established in the art of the memory devices.
Claims 6-8 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wu (US 2010/0182865) in view of M Siddiqui et al. (US 12,243,585).
Regarding claims 6-8, Wu teaches the limitations of claim 5.
Wu does not explicitly disclose the pre-driver receives a clock signal to generate a processed signal, and the post-driver receives the processed signal to generate an output clock signal serving as the global IO signal to the IO circuitry; a signal generator supplied by the first supply voltage, configured to generate a first clock signal; and a level shift circuit, configured to receive the first clock signal to generate the clock signal, wherein a voltage level of the clock signal is higher than a voltage level of the first clock signal; and each of the pre-driver and the post-driver comprises an inverter.
M Siddiqui et al. teach the deficiencies, in FIGS. 2, 4-5 and 7, and accompanying disclosure.
Wu and M Siddiqui are analogous art because they both are directed to SRAM write assist and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wu with the specified features of M Siddiqui because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of M Siddiqui et al. to the teaching of Wu such that a memory, as taught by Wu, utilizes a clocked driver circuitry in a multi-power domain, as taught by M Siddiqui et al., for the purpose of enhancing memory write operation, and further these conventional technology are well established in the art of the memory devices.
Response to Arguments
Applicant’s arguments filed 10/28/2025, with respect to the rejection(s) of claims 1-9 under 35 USC 102 and 103, have been fully considered but are not persuasive.
The applicant argus that Wu fails to explicitly teach the claimed limitation “the negative voltage provider and the NBL timing control circuit are supply by the second supply voltage”.
In response to the applicant’s argument, the examiner corrected typographical error and updated the description of Wu’s teaching to clearly and reflect the limitations of claims. See the art rejection revised above for more details.
Specifically, the applicant’s claim is open-ended. From SC1/SC2, through IN1/2, to INV1/2, to read on claimed the NBL timing control circuit are supplied by high voltage source.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825