DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 10-11, 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2018/0053788 A1 hereinafter referred to as “Lee”).
With respect to claim 1, Lee discloses, in Figs.1-13, a pixel structure, comprising: a substrate (100); an active device (TFT) disposed on the substrate (100) (see Par.[0040]-[0041] wherein a buffer layer 110 may be disposed on the substrate 100; a thin film transistor (TFT) may be disposed on the buffer layer 110); a planarization layer (180) disposed on the substrate (100) and covering the active device (TFT); a pixel electrode (185) disposed on the planarization layer (180) and electrically connected to the active device (TFT) (see Par.[0052]-[0053] wherein the pixel electrode 185 may be disposed on the source/drain electrodes 150 and 160; the passivation layer 180 may be disposed between the source/drain electrodes 150 and 160 and the pixel electrode 185); and a patterned protection layer (210) disposed on the planarization layer (180) and laterally surrounding the pixel electrode (185), wherein both the patterned protection layer (210) and the pixel electrode (185) are in contact with the planarization layer (180) (see Fig.3, Par.[0058] wherein a pixel defining layer 210 may be disposed on the passivation layer 180; the pixel defining layer 210 may partially cover the pixel electrode 185; for example, the pixel defining layer 210 may cover an edge portion of the pixel electrode 185, and may expose a center portion of the pixel electrode 185).
With respect to claim 2, Lee discloses, in Figs.1-13, the pixel structure, wherein the patterned protection layer (210) has an opening, and the pixel electrode (185) overlaps an area of the opening (see Figs.12-13).
With respect to claim 3, Lee discloses, in Figs.1-13, the pixel structure, wherein an outline of the opening is substantially aligned with an outline of the pixel electrode (see Figs.12-13).
With respect to claim 6, Lee discloses, in Figs.1-13, the pixel structure, wherein the patterned protection layer (210) partially overlaps a periphery of the pixel electrode (185) (see Figs.12-13).
With respect to claim 7, Lee discloses, in Figs.1-13, the pixel structure, wherein a material of the patterned protection layer (210) comprises an organic insulation material (see Par.[0094] wherein the pixel defining layer 210 may be formed of a polyimide based resin, a photoresist, an acrylic based resin, a polyamide based resin, a siloxane based resin, or the like. These may be used alone or a combination thereof).
With respect to claim 8, Lee discloses, in Figs.1-13, the pixel structure, wherein the pixel electrode (185) and the patterned protection layer (210) completely cover the planarization layer (180) (see Figs.12-13).
With respect to claim 10, Lee discloses, in Figs.1-13, a manufacturing method of a pixel structure, comprising: forming an active device (TFT) on a substrate (100) (see step of Fig.4, Par.[0040]-[0041] wherein a buffer layer 110 may be disposed on the substrate 100; a thin film transistor (TFT) may be disposed on the buffer layer 110); forming a planarization layer (180) on the substrate (100) to cover the active device (TFT) (see step of Fig.5, Par.[0052]-[0053] wherein the pixel electrode 185 may be disposed on the source/drain electrodes 150 and 160; the passivation layer 180 may be disposed between the source/drain electrodes 150 and 160 and the pixel electrode 185); forming a pixel electrode (185) on the planarization layer (180) by using a common photomask (300) (see step of Figs.8-11, Par.[0085]-[0086] wherein the first pixel electrode layer 190′ may be formed between the second layer 172 of the pad electrode 170 and the second pixel electrode layer 200′ as described above; a photoresist pattern 300 may be formed on the second pixel electrode layer 200′; the photoresist pattern 300 may correspond to a region in which the pixel electrode 185 is formed); and forming a patterned protection layer (210) on the planarization layer by using the common photomask, wherein the patterned protection layer (210) laterally surrounds the pixel electrode (185) (see steps of Figs.10-13, Par.[0058] wherein a pixel defining layer 210 may be disposed on the passivation layer 180; the pixel defining layer 210 may partially cover the pixel electrode 185; for example, the pixel defining layer 210 may cover an edge portion of the pixel electrode 185, and may expose a center portion of the pixel electrode 185; deposition of PDL 210 includes using photo resist mask 300 to removed pixel electrode to exposed an area of deposition).
With respect to claim 11, Lee discloses, in Figs.1-13, the manufacturing method of the pixel structure, wherein a method of forming the pixel electrode comprises: forming a conductive material layer (200’, 190’) and a first photoresist layer (300) on the planarization layer (180); patterning the first photoresist layer into a first photoresist pattern (300) by using the common photomask; and patterning the conductive material layer (200’, 190’) into the pixel electrode (185) by using the first photoresist pattern as a mask (see steps of Figs.8-9).
With respect to claim 14, Lee discloses, in Figs.1-13, the manufacturing method of the pixel structure, wherein a method of forming the patterned protection layer (210) comprises: forming a photosensitive insulation material layer on the planarization layer; and patterning the photosensitive insulation material layer into the patterned protection layer by using the common photomask (see Figs.8-12).
Claims 1-8, 10-12, 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choe et al. (US 2017/0040397 A1 hereinafter referred to as “Choe”).
With respect to claim 1, Choe discloses, in Figs.1-14, a pixel structure, comprising: a substrate (100); an active device (TFT) disposed on the substrate (100); a planarization layer (170) disposed on the substrate (100) and covering the active device (TFT) (see Par.[0047] wherein a thin-film transistor TFT or a capacitor Cap may be formed on the substrate 100; the planarization layer 170 that may cover the thin-film transistor TFT and may have an approximately flat top surface); a pixel electrode (210) disposed on the planarization layer (170) and electrically connected to the active device (TFT) (see Par.[0043]-[0044] wherein the backplane may be understood as including at least a substrate 100, pixel electrodes 210R, 210G, and 210B formed on the substrate 100); and a patterned protection layer (180) disposed on the planarization layer (170) and laterally surrounding the pixel electrode (210), wherein both the patterned protection layer (180) and the pixel electrode (210) are in contact with the planarization layer (170) (see Par.[0046] wherein the pixel definition layer 180 may include various materials, for example, an inorganic material, such as, silicon nitride, silicon oxide, or silicon oxynitride, and an organic material, such as, acryl or polyimide).
With respect to claim 2, Choe discloses, in Figs.1-14, the pixel structure, wherein the patterned protection layer (180) has an opening, and the pixel electrode (210) overlaps an area of the opening (see Fig.1).
With respect to claim 3, Choe discloses, in Figs.1-14, the pixel structure, wherein an outline of the opening is substantially aligned with an outline of the pixel electrode (210) (see Fig.1).
With respect to claim 4, Choe discloses, in Figs.1-14, the pixel structure, wherein a material of the patterned protection layer (180) comprises an inorganic insulation material (see Par.[0046] wherein the pixel definition layer 180 may include various materials, for example, an inorganic material, such as, silicon nitride, silicon oxide, or silicon oxynitride, and an organic material, such as, acryl or polyimide).
With respect to claim 5, Choe discloses, in Figs.1-14, the pixel structure, wherein a material of the patterned protection layer (180) comprises silicon nitride (see Par.[0046] wherein the pixel definition layer 180 may include various materials, for example, an inorganic material, such as, silicon nitride, silicon oxide, or silicon oxynitride, and an organic material, such as, acryl or polyimide).
With respect to claim 6, Choe discloses, in Figs.1-14, the pixel structure, wherein the patterned protection layer (180) partially overlaps a periphery of the pixel electrode (210) (see Fig.1).
With respect to claim 7, Choe discloses, in Figs.1-14, the pixel structure, wherein a material of the patterned protection layer (180) comprises an organic insulation material (see Par.[0046] wherein the pixel definition layer 180 may include various materials, for example, an inorganic material, such as, silicon nitride, silicon oxide, or silicon oxynitride, and an organic material, such as, acryl or polyimide).
With respect to claim 8, Choe discloses, in Figs.1-14, the pixel structure, wherein the pixel electrode (210) and the patterned protection layer (180) completely cover the planarization layer (170) (see Fig.1).
With respect to claim 10, Choe discloses, in Figs.1-14, a manufacturing method of a pixel structure, comprising: forming an active device (TFT) on a substrate (100); forming a planarization layer (170) on the substrate (100) to cover the active device (TFT) (see Par.[0047] wherein a thin-film transistor TFT or a capacitor Cap may be formed on the substrate 100; the planarization layer 170 that may cover the thin-film transistor TFT and may have an approximately flat top surface); forming a pixel electrode (210) on the planarization layer (170) by using a common photomask (191, 193); and forming a patterned protection layer (180, 191a, 193a) on the planarization layer (170) by using the common photomask (191, 193), wherein the patterned protection layer (180, 191a, 193a) laterally surrounds the pixel electrode (210) (see steps of Figs.2-4, Par.[0048]-[0049] wherein as shown in FIG. 3, a portion of the photoresist layer 193 may be exposed and developed, and a patterned photoresist layer 193 a may be formed on a portion of the sacrificial layer 191 from which a patterned sacrificial layer 191a may be formed; by patterning the sacrificial layer 191 by using the patterned photoresist layer 193a as a mask, the patterned sacrificial layer 191a may be formed).
With respect to claim 11, Choe discloses, in Figs.1-14, the manufacturing method of the pixel structure, wherein a method of forming the pixel electrode comprises: forming a conductive material layer and a first photoresist layer on the planarization layer; patterning the first photoresist layer into a first photoresist pattern by using the common photomask; and patterning the conductive material layer into the pixel electrode by using the first photoresist pattern as a mask (see Figs.2-4).
With respect to claim 12, Choe discloses, in Figs.1-14, the manufacturing method of the pixel structure, wherein a method of forming the patterned protection layer comprises: forming an insulation material layer (180) and a second photoresist layer (191a, 193a) on the planarization layer (170); patterning the second photoresist layer into a second photoresist pattern by using the common photomask; and patterning the insulation material layer into the patterned protection layer by using the second photoresist pattern as a mask (see Figs.2-4).
With respect to claim 14, Choe discloses, in Figs.1-14, the manufacturing method of the pixel structure, wherein a method of forming the patterned protection layer comprises: forming a photosensitive insulation material layer on the planarization layer; and patterning the photosensitive insulation material layer into the patterned protection layer by using the common photomask (see Figs.2-4).
Claims 1-3, 6, 8-12, 14, 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (US 2021/0376003 A1 hereinafter referred to as “Xu”).
With respect to claim 1, Xu discloses, in Figs.1-27, a pixel structure, comprising: a substrate (10); an active device (401) disposed on the substrate (10) (see Par.[0083]-[0084] wherein a pattern of a drive structure layer 401 is manufactured on the flexible base substrate 10; the drive structure layer 401 includes multiple gate lines and multiple data lines, and the multiple gate lines and the multiple data lines vertically intersect with each other to define multiple pixel units disposed in a matrix, each pixel unit includes at least three sub-pixels, and each sub-pixel includes at least one first Thin Film Transistor (TFT)); a planarization layer (19) disposed on the substrate (10) and covering the active device (401); a pixel electrode (20) disposed on the planarization layer (19) and electrically connected to the active device (401) (see Par.[0065]-[0066] wherein the first planarization layer 19 is disposed on the drive structure layer 401; the first electrode 20 is disposed on the first planarization layer 19 and connected to the first thin film transistor in the drive structure layer 401 through a via hole provided on the first planarization layer 19); and a patterned protection layer (21) disposed on the planarization layer (19) and laterally surrounding the pixel electrode (20), wherein both the patterned protection layer (21) and the pixel electrode (20) are in contact with the planarization layer (19).
With respect to claim 2, Xu discloses, in Figs.1-27, the pixel structure, wherein the patterned protection layer (21) has an opening, and the pixel electrode (20) overlaps an area of the opening (see Figs.10-12).
With respect to claim 3, Xu discloses, in Figs.1-27, the pixel structure, wherein an outline of the opening is substantially aligned with an outline of the pixel electrode (21) (see Figs.10-12).
With respect to claim 6, Xu discloses, in Figs.1-27, the pixel structure, wherein the patterned protection layer (21) partially overlaps a periphery of the pixel electrode (20) (see Figs.10-12).
With respect to claim 8, Xu discloses, in Figs.1-27, the pixel structure, wherein the pixel electrode and the patterned protection layer (21) completely cover the planarization layer (20) (see Figs.10-12).
With respect to claim 9, Xu discloses, in Figs.1-27, the pixel structure, further comprising a functionality layer (35-37) disposed on the substrate (10), wherein the functionality layer (35-37) and the active device (401) are positioned on two opposite sides of the substrate (10) (see Fig.1, Par.[0064], [0067]-[0068], [0080]-[0081] wherein the fingerprint identification sensor 35 may be a Charge Coupled Device (CCD) image sensor, a Complementary Metal Oxide Semiconductor (CMOS) image sensor, or a Positive Intrinsic Negative (PIN)-type photoelectric sensor manufactured by an amorphous silicon process; see Par.[0100]-[0101] wherein a fingerprint identification sensor 35 is attached to a surface of the base film 2 away from the flexible base substrate 10, the fingerprint identification sensor 35 is attached to the surface of the base film 2 on the side away from the flexible base substrate 10 through a foam layer 36 and the fingerprint identification sensor 35 is connected to a flexible printed circuit (FPC) 37, as shown in FIG. 1).
With respect to claim 10, Xu discloses, in Figs.1-27, a manufacturing method of a pixel structure, comprising: forming an active device (401) on a substrate (10) (see step of Figs.6-7, Par.[0083]-[0084] wherein a pattern of a drive structure layer 401 is manufactured on the flexible base substrate 10; the drive structure layer 401 includes multiple gate lines and multiple data lines, and the multiple gate lines and the multiple data lines vertically intersect with each other to define multiple pixel units disposed in a matrix, each pixel unit includes at least three sub-pixels, and each sub-pixel includes at least one first Thin Film Transistor (TFT)); forming a planarization layer (19) on the substrate (10) to cover the active device (401) (see step of Fig.8, Par.[0065]-[0066] wherein the first planarization layer 19 is disposed on the drive structure layer 401; the first electrode 20 is disposed on the first planarization layer 19 and connected to the first thin film transistor in the drive structure layer 401 through a via hole provided on the first planarization layer 19); forming a pixel electrode (20) on the planarization layer (19) by using a common photomask (see step of Fig.9, Par.[0092] wherein forming the pattern of the first electrode 20 includes depositing a fourth metal thin film on the base substrate where the above patterns are formed, coating a layer of photoresist on the fourth metal thin film, exposing the photoresist with a single tone mask, forming an unexposed area at the position of the first electrode 20, forming fully exposed areas at other positions, developing and removing the photoresist in the fully exposed areas, etching off the fourth metal film in the fully exposed areas, and stripping off the photoresist to form the pattern of the first electrode 20, as shown in FIG. 9); and forming a patterned protection layer (21) on the planarization layer (19) by using the common photomask, wherein the patterned protection layer laterally surrounds the pixel electrode (20) (see step of Fig.10 Par.[0093] wherein a pixel define thin film is coated on the base substrate where the above patterns are formed, and a pattern of a pixel define layer (PDL) 21 is formed through masking, exposure and development processes, wherein the pixel define layer 21 is provided thereon with pixel openings, and the pixel define thin film in the pixel openings is developed away to expose a surface of the first electrode 20; the pixel define layer 21 is provided with a first opening K1, and the pixel define thin film in the first opening K1 is developed to expose a surface of the first planarization layer 19, as shown in FIG. 10).
With respect to claim 11, Xu discloses, in Figs.1-27, the manufacturing method of the pixel structure, wherein a method of forming the pixel electrode (20) comprises: forming a conductive material layer and a first photoresist layer on the planarization layer; patterning the first photoresist layer into a first photoresist pattern by using the common photomask; and patterning the conductive material layer into the pixel electrode by using the first photoresist pattern as a mask (see step of Fig.9, Par.[0092] wherein forming the pattern of the first electrode 20 includes depositing a fourth metal thin film on the base substrate where the above patterns are formed, coating a layer of photoresist on the fourth metal thin film, exposing the photoresist with a single tone mask, forming an unexposed area at the position of the first electrode 20, forming fully exposed areas at other positions, developing and removing the photoresist in the fully exposed areas, etching off the fourth metal film in the fully exposed areas, and stripping off the photoresist to form the pattern of the first electrode 20, as shown in FIG. 9).
With respect to claim 12, Xu discloses, in Figs.1-27, the manufacturing method of the pixel structure, wherein a method of forming the patterned protection layer (21) comprises: forming an insulation material layer and a second photoresist layer on the planarization layer; patterning the second photoresist layer into a second photoresist pattern by using the common photomask; and patterning the insulation material layer into the patterned protection layer by using the second photoresist pattern as a mask (see step of Fig.10 Par.[0093] wherein a pixel define thin film is coated on the base substrate where the above patterns are formed, and a pattern of a pixel define layer (PDL) 21 is formed through masking, exposure and development processes, wherein the pixel define layer 21 is provided thereon with pixel openings, and the pixel define thin film in the pixel openings is developed away to expose a surface of the first electrode 20; the pixel define layer 21 is provided with a first opening K1, and the pixel define thin film in the first opening K1 is developed to expose a surface of the first planarization layer 19, as shown in FIG. 10; it is submitted that in semiconductor display pixel definition layer is of bank insulative material).
With respect to claim 14, Xu discloses, in Figs.1-27, the manufacturing method of the pixel structure, wherein a method of forming the patterned protection layer comprises: forming a photosensitive insulation material layer on the planarization layer; and patterning the photosensitive insulation material layer into the patterned protection layer by using the common photomask (see step of Fig.9, Par.[0092] wherein forming the pattern of the first electrode 20 includes depositing a fourth metal thin film on the base substrate where the above patterns are formed, coating a layer of photoresist on the fourth metal thin film, exposing the photoresist with a single tone mask, forming an unexposed area at the position of the first electrode 20, forming fully exposed areas at other positions, developing and removing the photoresist in the fully exposed areas, etching off the fourth metal film in the fully exposed areas, and stripping off the photoresist to form the pattern of the first electrode 20, as shown in FIG. 9).
With respect to claim 17, Xu discloses, in Figs.1-27, the manufacturing method of the pixel structure, further comprising forming a functionality layer (2, 35-37) on the substrate, wherein the functionality layer and the active device are positioned on two opposite sides of the substrate (see Fig.1, Par.[0064], [0067]-[0068], [0080]-[0081] wherein the fingerprint identification sensor 35 may be a Charge Coupled Device (CCD) image sensor, a Complementary Metal Oxide Semiconductor (CMOS) image sensor, or a Positive Intrinsic Negative (PIN)-type photoelectric sensor manufactured by an amorphous silicon process; see Par.[0100]-[0101] wherein a fingerprint identification sensor 35 is attached to a surface of the base film 2 away from the flexible base substrate 10, the fingerprint identification sensor 35 is attached to the surface of the base film 2 on the side away from the flexible base substrate 10 through a foam layer 36 and the fingerprint identification sensor 35 is connected to a flexible printed circuit (FPC) 37, as shown in FIG. 1).
Claims 1-3, 6-8, 10-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0359048 A1 hereinafter referred to as “Kim”).
With respect to claim 1, Kim discloses, in Figs.1-12, a pixel structure, comprising: a substrate (100); an active device (TFT) disposed on the substrate (100) (see Par.[0082]-[0083] wherein the display apparatus may include a substrate 100, a pixel circuit layer PCL on the substrate 100, and a display element layer DEL on the pixel circuit layer PCL; the pixel circuit layer PCL may include at least one thin-film transistor TFT); a planarization layer (119) disposed on the substrate (100) and covering the active device (TFT) (see Par.[0083] wherein a planarization layer 119, which are arranged under or/and above elements of the thin-film transistor TF); a pixel electrode (LE) disposed on the planarization layer (119) and electrically connected to the active device (TFT) (see Par.[0095]-[0096] wherein the connection electrode LE may be between the pixel circuit layer PCL and the organic light-emitting diode OLED); and a patterned protection layer (BL1, BL2) disposed on the planarization layer (119) and laterally surrounding the pixel electrode (LE), wherein both the patterned protection layer (BL1, BL2) and the pixel electrode (LE) are in contact with the planarization layer (119) (see Par.[0116] wherein the second bank layer BL2 may include a photoresist, that is, a photosensitive resin. Specifically, the second bank layer BL2 may include a negative photoresist; for example, the second bank layer BL2 may include an epoxy-based polymer or an off-stoichiometry thiolenes (OSTE) polymer; the material of the second bank layer BL2 may be relatively higher in molecular weight than the material of the first bank layer BL1; similarly to the first bank layer BL1, the second bank layer BL2 may include a positive photoresist).
With respect to claim 2, Kim discloses, in Figs.1-12, the pixel structure, wherein the patterned protection layer (BL1, BL2) has an opening, and the pixel electrode (LE) overlaps an area of the opening (see Figs.4A-4B, 5).
With respect to claim 3, Kim discloses, in Figs.1-12, the pixel structure, wherein an outline of the opening is substantially aligned with an outline of the pixel electrode (LE) (see Figs.4A-4B, 5).
With respect to claim 6, Kim discloses, in Figs.1-12, the pixel structure, wherein the patterned protection layer (BL1, BL2) partially overlaps a periphery of the pixel electrode (LE) (see Figs.4A-4B, 5).
With respect to claim 7, Kim discloses, in Figs.1-12, the pixel structure, wherein a material of the patterned protection layer (BL1, BL2) comprises an organic insulation material (see Par.[0102] wherein the first bank layer BL1 may include diazonaphthoquinones, maleic anhydride/norbornene copolymer, hydroxystyrene/acrylate copolymer, or methacrylate copolymer; as another example, the first bank layer BL1 may include at least one of diazonaphthoquinone (DNQ) and a novolac resin; see Par.[0116] wherein the second bank layer BL2 may include a photoresist, that is, a photosensitive resin; specifically, the second bank layer BL2 may include a negative photoresist. For example, the second bank layer BL2 may include an epoxy-based polymer or an off-stoichiometry thiolenes (OSTE) polymer).
With respect to claim 8, Kim discloses, in Figs.1-12, the pixel structure, wherein the pixel electrode (LE) and the patterned protection layer (BL1, BL2) completely cover the planarization layer (119) (see Figs.4A-4B, 5).
With respect to claim 10, Kim discloses, in Figs.1-12, a manufacturing method of a pixel structure, comprising: forming an active device (TFT) on a substrate (100); forming a planarization layer (119) on the substrate (100) to cover the active device (TFT); forming a pixel electrode (LE) on the planarization layer (119) by using a common photomask (M1-M2, L1, HM) (see steps of Fig.6B-6D, Par.[0135]-[0138] wherein the first photoresist layer L1 may include a positive photoresist; the first photoresist layer L1 may be formed by applying a positive photoresist liquid to the pixel circuit layer PCL through various methods such as spin-coating, spraying, or immersion; see Figs.8A-8B, Par.[0160]-[0164] wherein a half-tone mask HM may be arranged on the first photoresist layer L1; the half-tone mask HM may control the amount of exposure applied to the first photoresist layer L1; for example, the half-tone mask HM may perform control such that the amount of exposure applied to the area in which the first bank area LP1 is to be formed is smaller than the amount of exposure applied to the area in which the first opening OP1 is to be formed. Also, the half-tone mask HM may perform control such that the amount of exposure applied to the second bank area LP2 is smaller than the amount of exposure applied to the area in which the first bank area LP1 is to be formed); and forming a patterned protection layer (BL1-BL2) on the planarization layer (119) by using the common photomask (M1, L1), wherein the patterned protection layer laterally surrounds the pixel electrode (LE) (see Fig.9, Par.[0165]-[0171] wherein a second bank layer BL2-1 may be arranged on the first bank layer BL1; the second bank layer BL2-1 may cover the end portion of the first electrode 121).
With respect to claim 11, Kim discloses, in Figs.1-12, the manufacturing method of the pixel structure, wherein a method of forming the pixel electrode comprises: forming a conductive material layer and a first photoresist layer on the planarization layer; patterning the first photoresist layer into a first photoresist pattern by using the common photomask; and patterning the conductive material layer into the pixel electrode by using the first photoresist pattern as a mask (see steps of Fig.6B-6D, Par.[0135]-[0138] wherein the first photoresist layer L1 may include a positive photoresist; the first photoresist layer L1 may be formed by applying a positive photoresist liquid to the pixel circuit layer PCL through various methods such as spin-coating, spraying, or immersion; see Figs.8A-8B, Par.[0160]-[0164] wherein a half-tone mask HM may be arranged on the first photoresist layer L1; the half-tone mask HM may control the amount of exposure applied to the first photoresist layer L1; for example, the half-tone mask HM may perform control such that the amount of exposure applied to the area in which the first bank area LP1 is to be formed is smaller than the amount of exposure applied to the area in which the first opening OP1 is to be formed. Also, the half-tone mask HM may perform control such that the amount of exposure applied to the second bank area LP2 is smaller than the amount of exposure applied to the area in which the first bank area LP1 is to be formed).
With respect to claim 12, Kim discloses, in Figs.1-12, the manufacturing method of the pixel structure, wherein a method of forming the patterned protection layer comprises: forming an insulation material layer and a second photoresist layer on the planarization layer; patterning the second photoresist layer into a second photoresist pattern by using the common photomask; and patterning the insulation material layer into the patterned protection layer by using the second photoresist pattern as a mask (see steps of Fig.6B-6D, Par.[0135]-[0138] wherein the first photoresist layer L1 may include a positive photoresist; the first photoresist layer L1 may be formed by applying a positive photoresist liquid to the pixel circuit layer PCL through various methods such as spin-coating, spraying, or immersion; see Figs.8A-8B, Par.[0160]-[0164] wherein a half-tone mask HM may be arranged on the first photoresist layer L1; the half-tone mask HM may control the amount of exposure applied to the first photoresist layer L1; for example, the half-tone mask HM may perform control such that the amount of exposure applied to the area in which the first bank area LP1 is to be formed is smaller than the amount of exposure applied to the area in which the first opening OP1 is to be formed. Also, the half-tone mask HM may perform control such that the amount of exposure applied to the second bank area LP2 is smaller than the amount of exposure applied to the area in which the first bank area LP1 is to be formed; see Fig.9, Par.[0165]-[0171] wherein a second bank layer BL2-1 may be arranged on the first bank layer BL1; the second bank layer BL2-1 may cover the end portion of the first electrode 121).
With respect to claim 13, Kim discloses, in Figs.1-12, the manufacturing method of the pixel structure, wherein the first photoresist layer is a positive photoresist and the second photoresist layer is a negative photoresist (see Par.[0154] wherein the first bank layer BL1 may be formed of a positive photoresist, and the second bank layer BL2 may be formed of a negative photoresist; the first bank layer BL1 is formed of a negative photoresist, the first angle A1 formed by the inner surface SSL1 of the first bank layer BL1 becomes relatively greater than that when the first bank layer BL1 is formed of a positive type photoresist).
With respect to claim 14, Kim discloses, in Figs.1-12, the manufacturing method of the pixel structure, wherein a method of forming the patterned protection layer comprises: forming a photosensitive insulation material layer on the planarization layer; and patterning the photosensitive insulation material layer into the patterned protection layer by using the common photomask (see steps of Fig.6B-6D, Par.[0135]-[0138] wherein the first photoresist layer L1 may include a positive photoresist; the first photoresist layer L1 may be formed by applying a positive photoresist liquid to the pixel circuit layer PCL through various methods such as spin-coating, spraying, or immersion; see Figs.8A-8B, Par.[0160]-[0164] wherein a half-tone mask HM may be arranged on the first photoresist layer L1; the half-tone mask HM may control the amount of exposure applied to the first photoresist layer L1; for example, the half-tone mask HM may perform control such that the amount of exposure applied to the area in which the first bank area LP1 is to be formed is smaller than the amount of exposure applied to the area in which the first opening OP1 is to be formed. Also, the half-tone mask HM may perform control such that the amount of exposure applied to the second bank area LP2 is smaller than the amount of exposure applied to the area in which the first bank area LP1 is to be formed).
With respect to claim 15, Kim discloses, in Figs.1-12, the manufacturing method of the pixel structure, wherein the first photoresist layer is a positive photoresist and the photosensitive insulation material layer is a negative photoresist (see Par.[0154] wherein the first bank layer BL1 may be formed of a positive photoresist, and the second bank layer BL2 may be formed of a negative photoresist; the first bank layer BL1 is formed of a negative photoresist, the first angle A1 formed by the inner surface SSL1 of the first bank layer BL1 becomes relatively greater than that when the first bank layer BL1 is formed of a positive type photoresist).
With respect to claim 16, Kim discloses, in Figs.1-12, the manufacturing method of the pixel structure, wherein the method of forming the patterned protection layer further comprises a baking operation to form a slope on an edge of the patterned protection layer (see Par.[0140] wherein the degree of adhesion with the pixel circuit layer PCL may be increased through a curing and drying process of the first bank layer BL1; the curing and drying process may include a heat treatment process. In this case, because the first bank layer BL1 employs a positive photoresist, the inner surface SSL1 of the first bank layer BL1 may have a gentle slope with respect to the upper surface of the substrate 100 even when the heat treatment process is performed thereon).
Citation of Pertinent prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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