DETAILED ACTION
The Amendment (RCE) filed July 29, 2026 has been entered. Claims 1-12 are pending. Claims 3-4 and 11 have been cancelled. Claims 11-12 have been added. Claims 1 and 6 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2022/0392513).
Regarding independent claim 1, Choi et al. disclose a memory device (see e.g., FIG. 2), comprising:
a memory array (130);
an input/output (IO) circuitry (230), configured to access the memory array; and
a control circuit (200, 300, 110-120), configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry;
wherein the IO circuitry is supplied by a first supply voltage (VDDL), the control circuit is supplied by at least a second supply voltage (VDDH) different from the first supply voltage;
wherein the IO circuitry comprises a sense amplifier (237) supplied by the first supply voltage (VDDL) and an output driver (238) wherein the sense amplifier is configured to read data from the memory array, and the output driver is configured to generate output data according to the data read by the sense amplifier;
wherein a voltage level of the second supply voltage (VDDH) is higher (see e.g., para. 0036: … VDDL, which is lower than … VDDH …) than a voltage level of the first supply voltage (VDDL), and the memory device further comprises a level shift circuit (320) configured to receive the first supply voltage to generate the second supply voltage (VDDL to VDDH).
Regarding dependent claims 2, 5 and 10, see Choi et al. e.g., FIG. 2 and accompanying disclosure.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5 and 10 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Campbell et al. (US 7,355,905) in view of e.g., Choi (US 2015/0063007).
Regarding independent claim 1, Campbell et al. teach a memory device, comprising:
a memory array (FIG. 2: 24);
an input/output (IO) circuitry (DIN/DOUT, along with FIG. 3: 38), configured to access the memory array; and
a control circuit (28), configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry;
wherein the IO circuitry is supplied by a first supply voltage (see FIG. 3: 38, VL), the control circuit is supplied by at least a second supply voltage (FIG. 2: 28, VM, col. 3, lines 53-55: … the control signal generator 28 are supplied by both the VM … supply voltages) different from the first supply voltage;
wherein the IO circuitry comprises a sense amplifier (FIG. 3: 38) supplied by the first supply voltage (VL) and an output driver (DOUT0, col. 7, lines 45-46: … the bit lines and amplifies the differential to produce the output bit Dout0) wherein the sense amplifier is configured to read data from the memory array, and the output driver is configured to generate output data according to the data read by the sense amplifier;
wherein a voltage level of the second supply voltage (VM) is higher than a voltage level of the first supply voltage (VL), and the memory device further comprises a level shift circuit (20) configured to receive the first supply voltage to generate the second supply voltage (VL to VM).
Campbell’s DOUT0 does not explicitly disclose an output driver as claimed.
However, “a data out (DOUT), such as that of Campbell, includes an output driver that drives the data read by the sense amplifier” is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Choi (US 2015/0063007), FIG. 2, INV in DOUT path.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Choi to the teaching of Campbell et al. such that a memory, as taught by Campbell et al., utilizes an output driver, as taught by Choi, for the purpose of driving signals to reliably transfer data from memory to external components, further these conventional technology are well established in the art of the memory devices.
Regarding claim 2, Campbell et al. and Choi, as combined, teach the limitations of claim 1.
Campbell et al. further teach the IO circuitry comprises a pre-charger, a write driver, and/or an input latch, and the global IO signal is an output clock signal generated by the control circuit (FIG. 2).
Regarding claim 5, Campbell et al. and Choi, as combined, teach the limitations of claim 1.
Campbell et al. further teach the control circuit is supplied by both the first supply voltage and the second supply voltage (FIG. 2).
Regarding claim 10, Campbell et al. and Choi, as combined, teach the limitations of claim 3.
Campbell et al. further teach the memory device is a dual-rail static random access memory (SRAM) circuitry (FIGS. 2-3).
Claims 6 and 9 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jain et al. (US 2019/0147942) in view of Chevallier (US 2018/0226972).
Regarding independent claim 6, Jain et al. teach a memory device (see e.g., FIGS. 3-4), comprising:
a memory array (100);
an input/output (IO) circuitry (180, 20, 186 and 188), configured to access the memory array; and
a control circuit (figure 3 except for a memory array and I/O), configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry;
wherein the IO circuitry is supplied by a first supply voltage (VDD domain), the control circuit is supplied by at least a second supply voltage (VDDM domain) different from the first supply voltage;
wherein a voltage level of the second supply voltage (VDDM domain) is higher than a voltage level of the first supply voltage (VDD domain)(see e.g., para. 0015: … VDD … higher voltage level VDDM …), and the control circuit is supplied by both the first supply voltage and the second supply voltage (see FIG. 4).
wherein the control circuit (figure 3 except for a memory array and I/O) comprises a pre-driver and a post-driver, the pre-driver is supplied by the second supply voltage and receives a clock signal (FIG. 3: CLK) to generate a processed signal (see FIGS. 3-4), and the post-driver is supplied by the first supply voltage and receives the processed signal to generate an output clock signal (FIG. 3: DCK) serving as the global IO signal to the IO circuitry (FIG. 3: 186 and 188).
Jain et al. are silent with respect to wherein the control circuit comprises a pre-driver and a post-driver, the pre-driver is supplied by the second supply voltage, and the post-driver is supplied by the first supply voltage.
Chevallier teaches the deficiencies in e.g., FIG. 9 and accompanying disclosure, e.g., para. 0042, i.e., the control circuit such as decoder comprises pre-driver (922) and post-driver (924), power domain 922 supplied by a high voltage supply, and power domain 924 supplied by low voltage supply.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Chevallier to the teaching of Jain et al. such that a memory, as taught by Jain et al., utilizes a dual-power driver, as taught by Chevallier, for the purpose of reducing overall leakage current (see Chevallier, paragraph [0042]).
Regarding claim 9, Jain et al. and Chevallier, as combined, teach the limitations of claim 6.
Jain et al. further teach each of the pre-driver and the post-driver comprises an inverter (FIG. 4).
Claims 6, 9 and 11-12 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jain et al. (US 2019/0147942) in view of Pilo (US 2023/0125268).
Regarding independent claim 6, Jain et al. teach a memory device (see e.g., FIGS. 3-4), comprising:
a memory array (100);
an input/output (IO) circuitry (180, 20, 186 and 188), configured to access the memory array; and
a control circuit (figure 3 except for a memory array and I/O), configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry;
wherein the IO circuitry is supplied by a first supply voltage (VDD domain), the control circuit is supplied by at least a second supply voltage (VDDM domain) different from the first supply voltage;
wherein a voltage level of the second supply voltage (VDDM domain) is higher than a voltage level of the first supply voltage (VDD domain)(see e.g., para. 0015: … VDD … higher voltage level VDDM …), and the control circuit is supplied by both the first supply voltage and the second supply voltage (see FIG. 4);
wherein the control circuit (figure 3 except for a memory array and I/O) comprises a pre-driver and a post-driver, the pre-driver is supplied by the second supply voltage and receives a clock signal (FIG. 3: CLK) to generate a processed signal (see FIGS. 3-4), and the post-driver is supplied by the first supply voltage and receives the processed signal to generate an output clock signal (FIG. 3: DCK) serving as the global IO signal to the IO circuitry (FIG. 3: 186 and 188).
Jain et al. are silent with respect to wherein the control circuit comprises a pre-driver and a post-driver, the pre-driver is supplied by the second supply voltage, and the post-driver is supplied by the first supply voltage.
Pilo teaches the deficiencies, i.e., the control circuit (e.g., FIG. 3: 111 and 300) comprises a pre-driver (302) and a post-driver (330), the pre-driver is supplied by the second supply voltage (para. 0060: 302 is also operated at VDDP voltage domain), and the post-driver is supplied by the first supply voltage (para. 0061: 330 operating at VDDA) (see also para. 0059: For example, a memory device … when VDDA is less than VDDP, and provide … when VDDA is greater than VDDP, i.e., here, VDDP is higher than VDDA).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Pilo to the teaching of Jain et al. such that a memory, as taught by Jain et al., utilizes a dual-power driver, as taught by Pilo, for the purpose of reducing overall leakage current, thereby improving power consumption.
Regarding claim 9, Jain et al. and Pilo, as combined, teach the limitations of claim 6.
Pilo further teaches each of the pre-driver and the post-driver comprises an inverter (FIG. 3).
Regarding claim 11, Jain et al. and Pilo, as combined, teach the limitations of claim 6.
Pilo further teaches the pre-driver comprises a first inverter (e.g., FIG. 3: 320) configured to receive a clock signal (116) to generate a processed signal having a voltage level of the second supply voltage (VDDP); and the post-driver comprises a second inverter (330) configured to receive the processed signal having the voltage level of the second supply voltage (VDDA) to generate an output clock signal serving as the global IO signal (319).
Regarding claim 12, Jain et al. and Pilo, as combined, teach the limitations of claim 11.
Pilo further teaches the output clock signal (e.g., FIG. 3: 319) serves as the global IO signal for an input latch (320) of the IO circuitry to sample an input data (see e.g., FIG. 3 and accompanying disclosure).
Claim 8 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Jain et al. (US 2019/0147942) in view of Chevallier (US 2018/0226972), and further in view of e.g., M Siddiqui et al. (US 12,243,585).
Regarding claim 8, Jain et al. and Chevallier, as combined, teach the limitations of claim 6.
Jain et al. do not explicitly disclose a signal generator supplied by the first supply voltage, configured to generate a first clock signal; a level shift circuit, configured to receive the first clock signal to generate the clock signal, wherein a voltage level of the clock signal is higher than a voltage level of the first clock signal.
However, claimed generating higher voltage level of clock signal by level shifter circuitry is a well-known technology for a type of memory control circuitry for its purpose.
For support, of the above asserted facts, see for example, M Siddiqui et al., FIG. 2: 212 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of M Siddiqui et al. to the teaching of Jain et al. and Chevallier, as combined, such that a memory, as taught by Jain et al. and Chevallier, utilizes dual-rail clock signals, as taught by M Siddiqui et al., for the purpose of utilizing multi power memory system, thereby enhancing memory operations, and further these conventional technology are well established in the art of the memory devices.
Response to Arguments
Applicant’s amendment filed 7/29/2026, with respect to the rejection(s) of claims 1-10 under 35 USC 102 and 103, have been fully considered but are not persuasive. See art rejections above for more details. Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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