DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Specifically, claim 2 is referring to a portion of claim 1 that has been removed with the current amendment.
The Examiner suggests cancelling claim 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR20180033645A).
Regarding independent claim 1, Kim teaches semiconductor structure (Fig. 2; para. 0039+), comprising:
a gate (200) (Fig. 2; para. 0039);
an active layer (400), disposed on the gate and having a source region, a drain region, and a channel region located between the source region and the drain region (Fig. 2; para. 0039);
a gate insulator layer (300), disposed between the gate and the active layer (Fig. 2; para. 0039);
a source (600), disposed above the source region and extending onto the gate insulator layer (Fig. 2; para. 0039); and
a drain (700), disposed above the drain region and extending onto the gate insulator layer (Fig. 2; para. 0039),
wherein
the gate insulator layer comprises a first gate insulator layer (lower 310), a second gate insulator layer (320), and a third gate insulator layer (upper 310), the second gate insulator layer is located between the first gate insulator layer and the third gate insulator layer (Fig. 2), and a material of the first gate insulator layer is the same as a material of the third gate insulator layer (para. 0045), while a material of the second gate insulator layer is different from the material of the first gate insulator layer (para. 0046),
wherein the first gate insulator layer has a first insulation thickness, the second gate insulator layer has a second insulation thickness, the third gate insulator layer has a third insulation thickness, and the second insulation thickness is less than the first insulation thickness and the third insulation thickness (Fig. 2; para. 0050-0051).
Kim is silent with respect to wherein the first insulation thickness is greater than the third insulation thickness; however, Kim provides that the first layer is thick enough to provide basic insulating properties (para. 0050) while the third layer is thick enough to reduce leakage current (para. 0048). That is, the thicknesses of each layer are result effective variables; therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the thicknesses of the layers to arrive at the claimed invention for the purpose of providing basic insulating properties and reduced leakage current to the TFT device (MPEP 2144.05).
Re claim 7, Kim teaches wherein a material of the first gate insulator layer and a material of the third gate insulator layer comprise silicon nitride, respectively (para. 0045).
Re claim 8, Kim teaches wherein the first gate insulator layer, the second gate insulator layer, and the third gate insulator layer are sequentially stacked on the gate (Fig. 2).
Re claim 9, Kim teaches wherein the first gate insulator layer, the second gate insulator layer, and the third gate insulator layer are arranged in a coplanar manner (Fig. 2).
Claim(s) 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR20180033645A) in view of Profijt et al (NPL-U on PTO-892).
Re claim 5, Kim teaches wherein the second gate insulator layer is may be an ALD layer, but is silent with respect to it being a “plasma treatment layer”.
Profijt teaches wherein plasma-assisted ALD is known to have benefits over conventional thermally-driven ALD such as improved material properties, etc (Section IV).
It would have been obvious to one of ordinary skill in the art at the time of filing to use plasma-assisted ALD as taught by Profijt to form the second gate insulator layer of Kim such that it was “a plasma treated layer” as claimed for the purpose of providing improved material properties of the layer.
Re claim 6, Kim in view Profijt teach wherein a material of the plasma treatment layer comprises titanium oxide (Kim para. 0046).
Claim(s) 1, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Moriguchi et al. (US Pub. 2010/0295047) in view of Kim et al. (KR20180033645A).
Regarding independent claim 1, Moriguchi teaches a semiconductor structure (Fig. 1; para. 0085+), comprising:
a gate (2) (para. 0086);
an active layer (4), disposed on the gate and having a source region, a drain region, and a channel region located between the source region and the drain region (Fig. 1; para. 0087);
a gate insulator layer (3), disposed between the gate and the active layer (Fig. 1; para. 0086);
a source (6a), disposed above the source region and extending onto the gate insulator layer (Fig. 1; para. 0091); and
a drain (6b), disposed above the drain region and extending onto the gate insulator layer (Fig. 1; para. 0091).
Moriguchi is silent with respect to the gate insulator layer comprising a first gate insulator layer, a second gate insulator layer, and a third gate insulator layer.
Kim teaches a semiconductor device wherein the gate insulator layer comprises a first gate insulator layer (lower 310), a second gate insulator layer (320), and a third gate insulator layer (upper 310), the second gate insulator layer is located between the first gate insulator layer and the third gate insulator layer (Fig. 2), and a material of the first gate insulator layer is the same as a material of the third gate insulator layer (para. 0045), while a material of the second gate insulator layer is different from the material of the first gate insulator layer (para. 0046),
wherein the first gate insulator layer has a first insulation thickness, the second gate insulator layer has a second insulation thickness, the third gate insulator layer has a third insulation thickness, and the second insulation thickness is less than the first insulation thickness and the third insulation thickness (Fig. 2; para. 0050-0051).
Kim is silent with respect to wherein the first insulation thickness is greater than the third insulation thickness; however, Kim provides that the first layer is thick enough to provide basic insulating properties (para. 0050) while the third layer is thick enough to reduce leakage current (para. 0048). That is, the thicknesses of each layer are result effective variables; therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize the thicknesses of the layers to arrive at the claimed invention for the purpose of providing basic insulating properties and reduced leakage current to the TFT device (MPEP 2144.05).
It would have been obvious to one of ordinary skill in the art at the time of filing to substitute the gate insulator structure of Moriguchi with the gate insulator structure of Kim to arrive at the claimed invention for the purpose of improving electron mobility characteristics of a thin film transistor during on driving and reducing leakage current of the device (Kim para. 0015).
Re claim 10, Moriguchi teaches an ohmic contact layer (5a, 5b), disposed between the source region of the active layer and the source and between the drain region of the active layer and the drain (para. 0090).
Re claim 11, Moriguchi teaches wherein a material of the active layer comprises amorphous silicon (para. 0087), and a first thickness of the active layer in the source region and a second thickness of the active layer in the drain region are respectively greater than a third thickness of the active layer in the channel region (Fig. 1).
Response to Arguments
The amendment to the title has been accepted.
Applicant's remaining arguments filed 06/29/2026 have been fully considered but they are not persuasive.
Specifically, Applicant argues Moriguchi is silent about the claimed features of "wherein the first gate insulator layer has a first insulation thickness, the second gate insulator layer has a second insulation thickness, the third gate insulator layer has a third insulation thickness, and the second insulation thickness is less than the first insulation thickness and the third insulation thickness, and the first insulation thickness is greater than the third insulation thickness" originally recited in the dependent claims 3 and 4, now clarified, and incorporated into the independent claim 1.
While the Examiner agrees with this statement, the Examiner notes that Moriguchi was not relied upon to teach this limitation.
Applicant argues Kim is silent with respect to the limitation of “the first insulation thickness is greater than the third insulation thickness”. Again, while the Examiner agrees with this statement, Kim was not relied upon to teach this feature explicitly. Kim was relied upon to make obvious this feature. That is, this limitation was/is rejected under 35 USC 103, not 35 U.S.C. 102(a)(1). As stated in the original rejection, Kim provides that the first gate insulator layer is to be thick enough to provide basic insulating properties (para. 0050) while the third gate insulator layer is to be thick enough to reduce leakage current (para. 0048). That is, the first gate insulator layer and the third gate insulator layer provide a different purpose wherein the thicknesses of both layers are result effective variables. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to optimize each layer thickness for purpose of providing the desired insulating and reduced leakage current to the device such that the claimed limitation of “the first insulation thickness is greater than the third insulation thickness” was arrived at. Refer also to MPEP 2144.05.
Applicant provides an explanation of how they arrived at the claimed specific thickness configuration and while it may or may not be different reasons than those made obvious by Kim, the Examiner notes that rationale different from Applicant’s in permissible (MPEP 2144, IV). This is, Kim makes obvious the claimed limitations regardless of whether the reasoning is the same or different from Applicant’s.
Applicant argues Profijit is silent with respect to the limitation of “the first insulation thickness is greater than the third insulation thickness”. Again, while the Examiner agrees with this statement, Profijit was not relied upon to teach this feature
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOLLY KAY REIDA whose telephone number is (571)272-4237. The examiner can normally be reached M-F 8:30-5:00PM.
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/MOLLY K REIDA/Examiner, Art Unit 2899
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