Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments filed 1/14/26 with respect to 12, 15-19, 21, 24-31 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yang et al.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12, 15-19, 21, 24-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanase et al. (U.S. Patent Publication No. 2015/0249133) in view of Yang et al. (U.S. Patent Publication No. 2021/0098398).
Referring to figures 3-6, Yanase et al. teaches an integrated circuit device formed on a semiconductor wafer, the integrated circuit device having a first depth, wherein, prior to singulation of the integrated circuit device from the semiconductor wafer, the integrated circuit device comprises:
a backside cut formed between the integrated circuit device and a second integrated circuit device (13) fabricated on the semiconductor wafers, the backside cut extending to within the first depth, but the backside cut not extending completely through the semiconductor wafer, wherein the backside cut exposes a plurality of edges of each of the integrated circuit devices (see figures 4a); and
a metallization layer (14) deposited on the backside of the wafer such that the integrated circuit device includes the metallization layer on a bottom surface of the integrated circuit device and on the edges of the integrated circuit device (see figure 4b, paragraph# 58).
However, the reference doesnot clearly teach a redistribution layer formed on a frontside of the integrated circuit device; and solder balls applied on the redistribution layer.
Yang et al. teaches an integrated circuit device having a redistribution layer (202) formed on a frontside of the integrated circuit device (200); and solder balls (124) applied on the redistribution layer (see figures 1-4).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form a redistribution layer formed on a frontside of the integrated circuit device and solder balls applied on the redistribution layer in Yanase et al. because it is known in the semiconductor packing to enhance electrical connection, reduced device size, and higher I/O density.
Regarding to claims 15, 24, the backside cut forms a backside trench between the integrated circuit device and the second integrated circuit device, the trench having a first saw lane width (see figure 5a).
Regarding to claims 16, 25, wherein in depositing the metallization layer, the metallization layer is deposited to a first thickness on the edges of the integrated circuit device (14, see figure 4, 5).
Regarding to claims 17, 26, 27, wherein, in singulating the integrated circuit devices from the wafer, the integrated circuit device has an integrated circuit device width that is aligned with the first thickness (see figure 5b).
Regarding to claims 18, 28, wherein, in singulating the integrated circuit devices from the wafer, the integrated circuit device has an integrated circuit device width that extends to wider than a width of the integrated circuit device at the edges plus the first thickness (see figure 5b).
Regarding to claims 19, 29, wherein after singulating the integrated circuit devices, each integrated circuit device includes a lip of metallized material in a same plane as the backside of the integrated circuit devices (see figures 5b, 6, 12).
Regarding to claim 21, a packaged integrated circuit device comprising:
a semiconductor wafer having a plurality of integrated circuit devices (13), each integrated circuit device extending into the semiconductor wafer to a first depth (see figure 3a-3b);
a backside cut formed on the semiconductor wafer in saw lanes between the integrated circuit devices, the backside cut extending to within the first depth and not extending completely through the semiconductor wafer, the backside cut exposing a plurality of sidewalls of each of the integrated circuit devices (see figure 4b); and
a metallization layer (14) deposited on the backside of the wafer such that each of the integrated circuit devices (13) includes the metallization layer on a bottom surface and on the exposed sidewalls of the integrated circuit device (see figure 4b).
However, the reference doesnot clearly teach a redistribution layer formed on a frontside of the integrated circuit device; and solder balls applied on the redistribution layer.
Yang et al. teaches an integrated circuit device having a redistribution layer (202) formed on a frontside of the integrated circuit device (200); and solder balls (124) applied on the redistribution layer (see figures 1-4).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would form a redistribution layer formed on a frontside of the integrated circuit device and solder balls applied on the redistribution layer in Yanase et al. because it is known in the semiconductor packing to enhance electrical connection, reduced device size, and higher I/O density.
Regarding to claim 30, the metallization layer deposited on the backside of the wafer includes titanium or titanium alloys (see paragraph# 58).
Claim 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanase et al. (U.S. Patent Publication No. 2015/0249133) in view of Yang et al. (U.S. Patent Publication No. 2021/0098398) as applied in claim(s) 12, 15-19, 21, 24-30 above in view of Kim et al. (U.S. Patent Publication No. 2019/0304927).
Referring to figures 3-6, Yanase et al. teaches an integrated circuit device formed on a semiconductor wafer, the integrated circuit device having a first depth, wherein, prior to singulation of the integrated circuit device from the semiconductor wafer, the integrated circuit device comprises:
a backside cut formed between the integrated circuit device and a second integrated circuit device (13) fabricated on the semiconductor wafers, the backside cut extending to within the first depth, but the backside cut not extending completely through the semiconductor wafer, wherein the backside cut exposes a plurality of edges of each of the integrated circuit devices (see figures 4a); and
a metallization layer (14) deposited on the backside of the wafer such that the integrated circuit device includes the metallization layer on a bottom surface of the integrated circuit device and on the edges of the integrated circuit device (see figure 4b, paragraph# 58).
However, the reference does not clearly teach the packaged integrated circuit device is characterized as a fan-out wafer level package (FOWLP) package type.
Kim et al. the packaged integrated circuit device is characterized as a fan-out wafer level package (FOWLP) package type (see paragraph# 107).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the packaged integrated circuit device is characterized as a fan-out wafer level package (FOWLP) package type in Yanase et al. as taught by Kim et al. because it is known in the art to form a semiconductor device with smaller package size and improved electrical performance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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