DETAILED ACTION
This office action is in response to the application filed on February 19, 2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/19/2024 and 8/30/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (EP 3,942,612) in view of Lee (US 2021/0036002).
With respect to Claim 1, Zhang discloses (Fig. 2,4O) most aspects of the current invention including an integrated circuit device comprising:
a peripheral circuit structure (portion 202); and a cell array structure (portion 204),
wherein the peripheral circuit structure includes:
a circuit board (201), a peripheral circuit (208) on the circuit board, a first insulating layer (ILD over 208) covering the circuit board and the peripheral circuit, and first bonding pads (211) on the first insulating layer and electrically connected to the peripheral circuit
wherein the cell array structure includes:
an insulating structure (234) having a first surface (lower surface of 234) and a second surface (upper surface of 234), the first surface facing the circuit board, the second surface being opposite to the first surface,
a plurality of gate electrode layers (216) spaced apart from each other in a vertical direction on the first surface of the insulating structure, and stacked in a step form,
a plurality of channel structures (224) passing through the plurality of gate electrode layers,
a cell contact plug (252) passing through at least a portion of the plurality of gate electrode layers (layers 252 passes through an upper surface portion of the plurality of gate electrode layers)
a first contact structure (246) and a second contact structure (248) laterally spaced apart from the plurality of gate electrode layers,
a common source line structure (layer 120 in Fig 1, layer 220 in Fig 2) conformally surrounding an upper portion of the plurality of channel structures (224)
a first wiring line (236-1) and a second wiring line (240) spaced apart from each other on the second surface of the insulating structure,
first conductive vias (242,232) passing through the insulating structure, connecting the common source line structure with the first wiring line (see via 232), and connecting the first contact structure with the first wiring line (see via 242),
a second conductive via (244) passing through the insulating structure and connecting the second contact structure with the second wiring line,
second bonding pads (213) connected to a lower portion of the plurality of channel structures, a lower portion of the cell contact plug, a lower portion of the first contact structure, and a lower portion of the second contact structure, and bonded to the first bonding pads
However, although Zhang discloses the common source line structure conformally surrounding an upper portion of the plurality of channel structures, Zhang does not disclose the common source line structure being inside the insulating structure.
On the other hand, and in the same field of endeavor, Lee ‘002 teaches (Fig 1-9) an integrated circuit device comprising a cell array structure that includes an insulating structure (95) having a first surface (lower surface of 95) and a second surface (upper surface of 95), a plurality of gate electrode layers (CP) spaced apart from each other in a vertical direction on the first surface of the insulating structure, a plurality of channel structures (CH) passing through the plurality of gate electrode layers and further comprising a common source line structure (CSL) conformally surrounding an upper portion of the plurality of channel structures and being inside the insulating structure (95). Lee ‘002 teaches this arrangement allows the insulating structure to serve as a protective insulating layer covering the common source line structure and further allows the common source line structure to be a conductive material to help prevent direct contact between the metal layer and a channel structure corresponding thereto and to prevent diffusion of metal into the channel structure (par 79).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the common source line structure being inside the insulating structure, in the device of Zhang, as taught by Lee ‘002 because this arrangement allows the insulating structure to serve as a protective insulating layer covering the common source line structure and further allows the common source line structure to be a conductive material to help prevent direct contact between the metal layer and a channel structure corresponding thereto and to prevent diffusion of metal into the channel structure.
With respect to Claim 2, Zhang discloses (Fig. 2,4O) wherein the common source line structure (layer 120 in Fig 1, layer 220 in Fig 2) has a square wave shape including a plurality of top surfaces, a plurality of bottom surfaces, a plurality of side surfaces connecting the plurality of top surfaces to the plurality of bottom surfaces such that the plurality of bottom surfaces are at a same vertical level (lower surfaces of layer 120 in Fig 1, layer 220 in Fig 2 at same level) and the plurality of top surfaces are at different vertical levels (upper surfaces of layer 120 in Fig 1, layer 220 in Fig 2 have surfaces at different levels)
With respect to Claim 3, Zhang discloses (Fig. 2,4O) wherein the common source line structure is a doped polysilicon layer. Furthermore, Lee ‘002 teaches (Fig 1-9) wherein the common source line structure (CSL) has a structure of one or more conductive layers that may consist of a doped polysilicon, a metal silicide, and a metal layer (par 79). Also, see comments stated above in Par. 9-10 with regards to Claim 1, which are considered repeated here.
With respect to Claim 4, Zhang discloses (Fig. 2,4O) wherein each of the first conductive vias (242,232) includes a barrier metal layer (outer layer of TiN) and an inner metal layer (metal/conductive layer), the first conductive via includes a first set of the first conductive vias that are connected to the common source line structure and a second set of the first conductive vias that are connected to the first contact structure. Furthermore, the barrier metal layer in each of the first set of the first conductive vias is in direct contact with the common source line structure, and the barrier metal layer of each of the second set of the first conductive vias is in direct contact with the first contact structure.
Furthermore, Lee ‘002 teaches (Fig 1-9) wherein the common source line structure (CSL) has a structure of one or more conductive layers that may consist of a doped polysilicon, a metal silicide, and a metal layer and this arrangement allows the common source line structure to be a conductive material to help prevent direct contact between the metal layer and a channel structure corresponding thereto and to prevent diffusion of metal into the channel structure. Also, see comments stated above in Par. 9-10 with regards to Claim 1, which are considered repeated here.
With respect to Claim 5, Zhang discloses (Fig. 2,4O) wherein a vertical length of the first conductive vias connecting the common source line structure with the first wiring line (i.e. first conductive vias 232) is less than a vertical length of the first conductive vias connecting the first contact structure with the first wiring line (i.e. first conductive vias 242).
However, it is noted that the specification fails to provide teachings about the criticality of wherein a vertical length of the first conductive vias connecting the common source line structure with the first wiring line is greater than a vertical length of the first conductive vias connecting the first contact structure with the first wiring line, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the first conductive vias disclosed by Zhang as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular first conductive vias lengths claimed by applicant is nothing more than one of numerous first conductive via shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
With respect to Claim 11, Zhang discloses (Fig. 2,4O) most aspects of the current invention including an integrated circuit device comprising:
an insulating structure (234) having a memory cell region (including channel portions 224), a connection region (stepped staircase portion) surrounding the memory cell region, and an outer pad region (portion comprising contact structures 246,248) surrounding the connection region;
a gate stack including a plurality of gate electrode layers (216) and a plurality of mold insulating layers (218), the plurality of gate electrode layers and the plurality of mold insulating layers extending in a horizontal direction and alternately stacked in a vertical direction on a bottom surface of the insulating structure, and the gate stack having a staircase structure in the connection region
a plurality of channel structures (224) passing through the gate stack in the vertical direction and extending to an inside of the insulating structure in the memory cell region
a word line cut (230) passing through the gate stack in the vertical direction in the memory cell region and the connection region, the word line cut extending to the inside of the insulating structure
a first contact structure (246) and a second contact structure (248) laterally spaced apart from the gate stack, in the outer pad region, the first contact structure and the second contact structure extending to the inside of the insulating structure
a common source line structure (layer 120 in Fig 1, layer 220 in Fig 2) conformally surrounding an upper portion of the plurality of channel structures (224) and an upper portion of the word line cut (230)
a first wiring line (236-1) extending along the memory cell region, the connection region, and the outer pad region on a top surface of the insulating structure;
a second wiring line (240) in the outer pad region and spaced apart from the first wiring line
first conductive vias (232,242) passing through the insulating structure, connecting the common source line structure with the first wiring line in the memory cell region (see via 232), and connecting the first contact structure with the first wiring line, in the outer pad region (see via 242),
a second conductive via (244) passing through the insulating structure and connecting the second contact structure with the second wiring line, in the outer pad region
However, although Zhang discloses the common source line structure conformally surrounding an upper portion of the plurality of channel structures, and an upper portion of the word line cut, Zhang does not disclose the common source line structure being inside the insulating structure.
On the other hand, and in the same field of endeavor, Lee ‘002 teaches (Fig 1-9) an integrated circuit device comprising a cell array structure that includes an insulating structure (95) having a first surface (lower surface of 95) and a second surface (upper surface of 95), a plurality of gate electrode layers (CP) spaced apart from each other in a vertical direction on the first surface of the insulating structure, a plurality of channel structures (CH) passing through the plurality of gate electrode layers and further comprising a common source line structure (CSL) conformally surrounding an upper portion of the plurality of channel structures and being inside the insulating structure (95). Lee ‘002 teaches this arrangement allows the insulating structure to serve as a protective insulating layer covering the common source line structure and further allows the common source line structure to be a conductive material to help prevent direct contact between the metal layer and a channel structure corresponding thereto and to prevent diffusion of metal into the channel structure (par 79).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the common source line structure being inside the insulating structure, in the device of Zhang, as taught by Lee ‘002 because this arrangement allows the insulating structure to serve as a protective insulating layer covering the common source line structure and further allows the common source line structure to be a conductive material to help prevent direct contact between the metal layer and a channel structure corresponding thereto and to prevent diffusion of metal into the channel structure.
With respect to Claim 12, Zhang discloses (Fig. 2,4O) wherein the common source line structure (layer 120 in Fig 1, layer 220 in Fig 2) has a square wave shape including a plurality of top surfaces, a plurality of bottom surfaces, a plurality of side surfaces connecting the plurality of top surfaces to the plurality of bottom surfaces such that the plurality of bottom surfaces are at a same vertical level (lower surfaces of layer 120 in Fig 1, layer 220 in Fig 2 at same level) and the plurality of top surfaces are at different vertical levels (upper surfaces of layer 120 in Fig 1, layer 220 in Fig 2 have surfaces at different levels) and wherein the common source line structure is a doped polysilicon layer. Furthermore, Lee ‘002 teaches (Fig 1-9) wherein the common source line structure (CSL) has a structure of one or more conductive layers that may consist of a doped polysilicon, a metal silicide, and a metal layer (par 79). Also, see comments stated above in Par. 20-21 with regards to Claim 11, which are considered repeated here.
With respect to Claim 13, Zhang discloses (Fig. 2,4O) wherein a vertical length of a first set of the first conductive vias connecting the common source line structure with the first wiring line (i.e. first conductive vias 232) is less than a vertical length of a second set of the first conductive vias connecting the first contact structure with the first wiring line (i.e. first conductive vias 242), and a vertical length of the second set of the first conductive vias connecting the first contact structure with the first wiring line is same as a vertical length of the second conductive via (i.e. second conductive vias 244).
However, it is noted that the specification fails to provide teachings about the criticality of wherein a vertical length of a first set of the first conductive vias connecting the common source line structure with the first wiring line is greater than a vertical length of a second set of the first conductive vias connecting the first contact structure with the first wiring line, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the first conductive vias disclosed by Zhang as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, as the particular first conductive vias lengths claimed by applicant is nothing more than one of numerous first conductive via shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
With respect to Claim 14, Zhang discloses (Fig. 2,4O) wherein the first wiring line and the second wiring line include aluminum, and the first conductive vias and the second conductive via include tungsten.
Claims 10, 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (EP 3,942,612) in view of Lee (US 2021/0036002) and in further view of Lee (US 2022/0037305).
With respect to Claim 10, Zhang in view of Lee ‘002 discloses most aspects of the present invention. However, the combination of references do not show wherein, when viewed in a plan view, a long axis direction of the first wiring line and a long axis direction of the second wiring line are orthogonal to each other, and an end of the first wiring line and a side of the second wiring line face each other and are spaced apart from each other.
On the other hand, and in the same field of endeavor, Lee ‘305 teaches (Fig 4-6B, 13) an integrated circuit device comprising a cell array structure that includes an insulating structure (173) having a first surface (lower surface of 173) and a second surface (upper surface of 173), a plurality of gate electrode layers (CP) spaced apart from each other in a vertical direction on the first surface of the insulating structure, a plurality of channel structures (CH) passing through the plurality of gate electrode layers and further comprising a common source line structure (CSL) conformally surrounding an upper portion of the plurality of channel structures and being inside the insulating structure (173), a first wiring line (71A) and a second wiring line (71B) spaced apart from each other on the second surface of the insulating structure, wherein, when viewed in a plan view, a long axis direction of the first wiring line and a long axis direction of the second wiring line are orthogonal to each other, and an end of the first wiring line and a side of the second wiring line face each other and are spaced apart from each other (par 70). Lee ‘305 teaches this arrangement improves the degree of arrangement freedom of lines (par 27).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of when viewed in a plan view, a long axis direction of the first wiring line and a long axis direction of the second wiring line are orthogonal to each other, and an end of the first wiring line and a side of the second wiring line face each other and are spaced apart from each other in the device of Zhang in view of Lee ‘002, as taught by Lee ‘305 because this arrangement improves the degree of arrangement freedom of lines.
With respect to Claim 15, Zhang in view of Lee ‘002 discloses most aspects of the present invention. However, the combination of references do not show wherein, when viewed in a plan view, an end of the first wiring line and a side of the second wiring line are spaced apart from each other while facing each other.
On the other hand, and in the same field of endeavor, Lee ‘305 teaches (Fig 4-6B, 13) an integrated circuit device comprising a cell array structure that includes an insulating structure (173) having a first surface (lower surface of 173) and a second surface (upper surface of 173), a plurality of gate electrode layers (CP) spaced apart from each other in a vertical direction on the first surface of the insulating structure, a plurality of channel structures (CH) passing through the plurality of gate electrode layers and further comprising a common source line structure (CSL) conformally surrounding an upper portion of the plurality of channel structures and being inside the insulating structure (173), a first wiring line (71A) and a second wiring line (71B) spaced apart from each other on the second surface of the insulating structure, wherein, when viewed in a plan view, an end of the first wiring line and a side of the second wiring line are spaced apart from each other while facing each other (par 70). Lee ‘305 teaches this arrangement improves the degree of arrangement freedom of lines (par 27).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of when viewed in a plan view, an end of the first wiring line and a side of the second wiring line are spaced apart from each other while facing each other in the device of Zhang in view of Lee ‘002, as taught by Lee ‘305 because this arrangement improves the degree of arrangement freedom of lines.
With respect to Claim 16, Lee ‘305 teaches (Fig 4-6B, 13) wherein, when viewed in a plan view, the first wiring line has a line shape extending in a first horizontal direction, and the second wiring line has a line shape extending in a second horizontal direction perpendicular to the first horizontal direction.
With respect to Claim 17, Lee ‘305 teaches (Fig 4-6B, 13) wherein, when viewed in a plan view, the first wiring line has a mesh shape extending in a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction, and the second wiring line has a line shape extending in the second horizontal direction (par 67,70)
With respect to Claim 18, Lee ‘305 teaches (Fig 4-6B, 13) wherein, when viewed in a plan view, the first wiring line has a rectangular plate shape, and the second wiring line has a rectangular pad shape.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (EP 3,942,612) in view of Lee (US 2021/0036002) and in further view of Hwang (US 2023/0005942).
With respect to Claim 19, Zhang discloses (Fig. 2,4O) most aspects of the current invention including an electronic system comprising an integrated circuit device (200), wherein the integrated circuit device includes:
a peripheral circuit structure (portion 202) including;
a circuit board (201), a peripheral circuit (208) on the circuit board, a first insulating layer (ILD over 208) covering the circuit board and the peripheral circuit, and first bonding pads (211) on the first insulating layer and electrically connected to the peripheral circuit
a cell array structure (portion 204) stacked on the peripheral circuit structure; the cell array structure includes:
an insulating structure (234) having a first surface (lower surface of 234) facing the circuit board and a second surface (upper surface of 234) opposite to the first surface,
a plurality of gate electrode layers (216) spaced apart from each other in a vertical direction on the first surface of the insulating structure, and stacked in a step form
a plurality of channel structures (224) passing through the plurality of gate electrode layers
a cell contact plug (252) passing through at least a portion of the plurality of gate electrode layers (layers 252 passes through an upper surface portion of the plurality of gate electrode layers)
a first contact structure (246) and a second contact structure (248) laterally spaced apart from the plurality of gate electrode layers
a common source line structure (layer 120 in Fig 1, layer 220 in Fig 2) conformally surrounding an upper portion of the plurality of channel structures (224)
a first wiring line (236-1) and a second wiring line (240) spaced apart from each other on the second surface of the insulating structure
first conductive vias (242,232) passing through the insulating structure, connecting the common source line structure with the first wiring line (see via 232), and connecting the first contact structure with the first wiring line (see via 242)
a second conductive via (244) passing through the insulating structure and connecting the second contact structure with the second wiring line
second bonding pads (213) connected to a lower portion of the plurality of channel structures, a lower portion of the cell contact plug, a lower portion of the first contact structure, and a lower portion of the second contact structure, and bonded to the first bonding pads
However, although Zhang discloses the common source line structure conformally surrounding an upper portion of the plurality of channel structures, Zhang does not disclose the electronic system comprising: a main substrate; the integrated circuit device on the main substrate; and a controller electrically connected to the integrated circuit device on the main substrate and Zhang further does not disclose the common source line structure inside the insulating structure.
On the other hand, and in the same field of endeavor, Lee ‘002 teaches (Fig 1-9) an integrated circuit device comprising a cell array structure that includes an insulating structure (95) having a first surface (lower surface of 95) and a second surface (upper surface of 95), a plurality of gate electrode layers (CP) spaced apart from each other in a vertical direction on the first surface of the insulating structure, a plurality of channel structures (CH) passing through the plurality of gate electrode layers and further comprising a common source line structure (CSL) conformally surrounding an upper portion of the plurality of channel structures and being inside the insulating structure (95). Lee ‘002 teaches this arrangement allows the insulating structure to serve as a protective insulating layer covering the common source line structure and further allows the common source line structure to be a conductive material to help prevent direct contact between the metal layer and a channel structure corresponding thereto and to prevent diffusion of metal into the channel structure (par 79).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the common source line structure being inside the insulating structure, in the device of Zhang, as taught by Lee ‘002 because this arrangement allows the insulating structure to serve as a protective insulating layer covering the common source line structure and further allows the common source line structure to be a conductive material to help prevent direct contact between the metal layer and a channel structure corresponding thereto and to prevent diffusion of metal into the channel structure.
However, the combination of references do not show the electronic system comprising: a main substrate; the integrated circuit device on the main substrate; and a controller electrically connected to the integrated circuit device on the main substrate.
On the other hand, and in the same field of endeavor, Hwang teaches (Fig 2,6) an electronic system (2000) comprising a main substrate (2001), an integrated circuit device (2003) on the main substrate and a controller (2002) electrically connected to the integrated circuit device on the main substrate. Hwang teaches the controller in the electronic system is used to write data in the semiconductor package (integrated circuit device) and/or read data from the semiconductor package (integrated circuit device) and may improve an operation speed of the electronic system (par 33).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the electronic system comprising: a main substrate; the integrated circuit device on the main substrate; and a controller electrically connected to the integrated circuit device on the main substrate in the device of Zhang and Lee ‘002, as taught by Hwang because the controller in the electronic system is used to write data in the semiconductor package (integrated circuit device) and/or read data from the semiconductor package (integrated circuit device) and may improve an operation speed of the electronic system.
With respect to Claim 20, Zhang discloses (Fig. 2,4O) wherein the common source line structure (layer 120 in Fig 1, layer 220 in Fig 2) has a square wave shape including a plurality of top surfaces, a plurality of bottom surfaces, a plurality of side surfaces connecting the plurality of top surfaces to the plurality of bottom surfaces such that the plurality of bottom surfaces are at a same vertical level (lower surfaces of layer 120 in Fig 1, layer 220 in Fig 2 at same level) and the plurality of top surfaces are at different vertical levels (upper surfaces of layer 120 in Fig 1, layer 220 in Fig 2 have surfaces at different levels) and wherein the common source line structure is a doped polysilicon layer. Furthermore, Lee ‘002 teaches (Fig 1-9) wherein the common source line structure (CSL) has a structure of one or more conductive layers that may consist of a doped polysilicon, a metal silicide, and a metal layer (par 79).
Additionally, Hwang teaches (Fig 2,6) wherein the main substrate comprises wiring patterns (2005) electrically connecting the integrated circuit device with the controller. Also, see comments stated above in Par. 40-44 with regards to Claim 19, which are considered repeated here.
Claim Objections
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUINTON A BRASFIELD whose telephone number is (571)272-0804. The examiner can normally be reached M-F 9AM-4PM.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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