DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species 1 (fig. 4; including Claims 1-4, 6, 9, 10-12, 14, 17-19) in the reply filed on 12/22/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. 20070013078.
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Regarding claim 1, figs. 6A-6B of Lee discloses a thin-film transistor comprising:
an active layer 40 on a substrate 10 and comprising a channel region, a source region connected to a side of the channel region, and a drain region connected to a different side of the channel region;
a gate insulating layer 30 on the channel region of the active layer; and
a gate electrode 115 on the gate insulating layer,
wherein a slope of each side surface of the gate electrode with respect to a boundary surface between the gate insulating layer and the gate electrode is an obtuse angle (solid line as labeled by examiner above), and
a slope of each side surface of the gate insulating layer with respect to the boundary surface between the gate insulating layer and the gate electrode is an obtuse angle (dotted line as labeled by examiner above).
Regarding claim 10 figs. 6A-6B of Lee discloses a transistor array substrate comprising:
a substrate 10 comprising a display area comprising subpixels (par [0005] - pixels); and
a circuit layer (see fig. 6B) on the substrate and comprising pixel drivers (each set of elements in fig. 6B) respectively corresponding to the subpixels,
wherein each of the pixel drivers comprises at least one thin-film transistor (see rejection of claim 1 as shown above), and
wherein at least one thin-film transistor of the circuit layer comprises:
an active layer on the substrate and comprising a channel region, a source region connected to a side of the channel region, and a drain region connected to a different side of the channel region;
a gate insulating layer on the channel region of the active layer; and
a gate electrode on the gate insulating layer, wherein
a slope of each side surface of the gate electrode with respect to a boundary surface between the gate insulating layer and the gate electrode is an obtuse angle, and
a slope of each side surface of the gate insulating layer with respect to the boundary surface between the gate insulating layer and the gate electrode is an obtuse angle.
Regarding claim 2, fig. 6B of Lee discloses wherein the active layer and the gate electrode are covered with an interlayer insulating layer 70 arranged substantially (relative term) flat on the substrate, and the gate electrode comprises: an electrode main layer 262; and an electrode barrier layer 263 between the electrode main layer and the gate insulating layer and between side surfaces (top left and top right side surfaces) of the electrode main layer and the interlayer insulating layer.
Regarding claims 11-12 (see claims 2-3 rejection), fig. 6B of Lee discloses wherein the circuit layer further comprises an interlayer insulating layer covering the active layer and the gate electrode and arranged substantially flat on the substrate, and the gate electrode comprises: an electrode main layer; and an electrode barrier layer between the electrode main layer and the gate insulating layer and between a side surface of the electrode main layer and a side surface of the interlayer insulating layer; wherein the electrode main layer comprises a single layer or a multilayer comprising at least one metal material selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more thereof, and the electrode barrier layer comprises a metal oxide material comprising one or more metal materials selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al) and molybdenum (Mo).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Yu et al. 20100052066.
Regarding claim 3, par [0062] of Lee discloses wherein the electrode main layer 262 comprises a single layer or a multilayer comprising copper (Cu).
Lee does not disclose that electrode barrier layer comprises a metal oxide material comprising one or more metal materials selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al) and molybdenum (Mo).
However, claims 1 and 4 of Yu discloses electrode barrier layer comprises a metal oxide material comprising one or more metal materials selected from the electrode barrier layer comprises a metal oxide material comprising one or more metal materials selected from indium (In), zinc (Zn), and tin (Sn).
In view of such teaching, it would have been obvious to form a transistor of Lee electrode barrier layer comprises a metal oxide material comprising one or more metal materials selected from the electrode barrier layer comprises a metal oxide material comprising one or more metal materials selected from indium (In), zinc (Zn), and tin (Sn) such as taught by Yu in order to have provide desired work function values and thermal stability.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Chen et al. 20160197128.
Regarding claim 4, Lee discloses claim 2, but does not disclose of wherein the active layer comprises an oxide semiconductor material comprising one or more metal materials selected from indium (In), gallium (Ga), zinc (Zn), tin (Sn), aluminum (Al) and molybdenum (Mo), and each of the source region and the drain region in the active layer is a conductor.
However, par [0003] of Chen discloses of active layer comprises an oxide semiconductor material comprising indium gallium zinc oxide (IGZO), and each of the source region and the drain region in the active layer is a conductor.
In view of such teaching, it would have been obvious to form a transistor of Lee comprising active layer comprises an oxide semiconductor material comprising indium gallium zinc oxide (IGZO), and each of the source region and the drain region in the active layer is a conductor such as taught by Chen in order to obtain a desired device characteristic.
Claims 6, 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of OH et al. 20230232691.
Regarding claims 6 and 14, Lee discloses claim 2, but does not disclose further comprising a light blocking layer on a first buffer layer covering the substrate and overlapping at least the channel region of the active layer, wherein the active layer is on a second buffer layer covering the light blocking layer.
However, fig. 6 of OH discloses a substrate 110, further comprising a light blocking layer BML on a first buffer layer 120 covering the substrate 110 and overlapping at least the channel region of the active layer ACT, wherein the active layer is on a second buffer layer 130 covering the light blocking layer.
In view of such teaching, it would have been obvious to form a transistor further comprising a light blocking layer on a first buffer layer covering the substrate and overlapping at least the channel region of the active layer, wherein the active layer is on a second buffer layer covering the light blocking layer such as taught by OH in order to protect transistor for the elements of the environment.
Regarding claim 9, par [0098] OH discloses wherein the light blocking layer comprises a single layer or a multilayer comprising at least one metal material selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of two or more thereof.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of OH in view of Kim et al. 20230064938 (Kim).
Regarding claim 17, fig. 12C of Lee discloses further comprising a light emitting element layer on the circuit layer and comprising light emitting elements electrically connected to the pixel drivers, wherein one of the pixel drivers is configured to transmit a driving current to one of the light emitting elements and comprises:
a first thin-film transistor connected in series to the light emitting element between a first power line and a second power line configured to transmit first power and second power for driving the light emitting elements (see fig. 6A).
Lee does not disclose of a second thin-film transistor electrically connected between a data line configured to transmit a data signal and a gate electrode of the first thin-film transistor and configured to be turned on based on a scan signal of a scan gate line; and
a pixel capacitor electrically connected to a first node between the gate electrode of the first thin-film transistor and the second thin-film transistor and a second node between the first thin-film transistor and the light emitting element, wherein a first electrode of the first thin-film transistor is electrically connected to the first power line, and a second electrode of the first thin-film transistor is electrically connected to an anode of the light emitting element.
However, fig. 3 of Kim discloses a circuit layer comprising a light emitting element layer on the circuit layer and the light emitting elements electrically connected to the pixel drivers, wherein one of the pixel drivers is configured to transmit a driving current to one of the light emitting elements and comprises:
a first thin-film transistor connected in series to the light emitting element between a first power line and a second power line configured to transmit first power and second power for driving the light emitting elements; a second thin-film transistor electrically connected between a data line configured to transmit a data signal and a gate electrode of the first thin-film transistor and configured to be turned on based on a scan signal of a scan gate line; and
a pixel capacitor electrically connected to a first node between the gate electrode of the first thin-film transistor and the second thin-film transistor and a second node between the first thin-film transistor and the light emitting element, wherein a first electrode of the first thin-film transistor is electrically connected to the first power line, and a second electrode of the first thin-film transistor is electrically connected to an anode of the light emitting element.
In view of such teaching, it would have been obvious to form a substrate of Lee and Oh a second thin-film transistor electrically connected between a data line configured to transmit a data signal and a gate electrode of the first thin-film transistor and configured to be turned on based on a scan signal of a scan gate line; and a pixel capacitor electrically connected to a first node between the gate electrode of the first thin-film transistor and the second thin-film transistor and a second node between the first thin-film transistor and the light emitting element, wherein a first electrode of the first thin-film transistor is electrically connected to the first power line, and a second electrode of the first thin-film transistor is electrically connected to an anode of the light emitting element such as taught by Kim in order to form a driver circuit.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of OH in view of Kim in view of Park et al. 20230200131.
Regarding claim 18, fig. 5 of Kim discloses wherein the circuit layer further comprises: a wiring conductive layer on the interlayer insulating layer; and a via layer arranged substantially flat on the interlayer insulating layer and covering the wiring conductive layer, wherein the wiring conductive layer comprises: the data line (source and drain line); the first power line (necessary the case that power is line is connected); a gate connection electrode 132 electrically connecting a gate electrode of the second thin-film transistor (that in SPA2 of fig. 5) and an anode connection electrode electrically connected to a source region of an active layer of the first thin-film transistor, and wherein the anode 211 is on the via layer and electrically connected to the anode connection electrode (electrode in 120).
Lee and OH and Kim does not disclose of a gate electrode electrically connecting a light blocking layer of the second thin-film transistor; and the anode connection electrode electrically connected to a light blocking layer of the first thin-film transistor.
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However, fig. 4 of Park disclose a gate electrode connecting a light blocking layer of the second thin-film transistor; and the anode connection electrode electrically connected to a light blocking layer of the first thin-film transistor.
In view of such teaching, it would have been obvious to from a transistor a gate electrode connecting a light blocking layer of the second thin-film transistor; and the anode connection electrode electrically connected to a light blocking layer of the first thin-film transistor in order to form a desire circuit.
In addition, it would have been obvious to form a substrate comprising the gate electrode electrically connecting a light blocking layer in order to obtain a same potential.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of OH in view of Kim in view of Park in view of Song et al. 20210376030.
Regarding claim 19, Lee and OH and Kim and Park claim 18, but do not disclose wherein the circuit layer further comprises: a first capacitor electrode on the first buffer layer; a second capacitor electrode on the second buffer layer and overlapping the first capacitor electrode; and a third capacitor electrode on the interlayer insulating layer and overlapping the second capacitor electrode, wherein the pixel capacitor is in an overlap area between each of the first capacitor electrode and the third capacitor electrode, the first capacitor electrode and the second capacitor electrode, and the second capacitor electrode and the third capacitor electrode.
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However, Song discloses a pixel capacitor comprises: a first capacitor electrode on the first buffer layer; a second capacitor electrode on the second buffer layer and overlapping the first capacitor electrode; and a third capacitor electrode on the interlayer insulating layer and overlapping the second capacitor electrode, wherein the pixel capacitor is in an overlap area between each of the first capacitor electrode and the third capacitor electrode, the first capacitor electrode and the second capacitor electrode, and the second capacitor electrode and the third capacitor electrode.
In view of such teaching, it would have been obvious to form a substrate further comprising wherein the circuit layer further comprises: a first capacitor electrode on the first buffer layer; a second capacitor electrode on the second buffer layer and overlapping the first capacitor electrode; and a third capacitor electrode on the interlayer insulating layer and overlapping the second capacitor electrode, wherein the pixel capacitor is in an overlap area between each of the first capacitor electrode and the third capacitor electrode, the first capacitor electrode and the second capacitor electrode, and the second capacitor electrode and the third capacitor electrode such as taught by Song in order to form three layer capacitor.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893