Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I in the reply filed on 11/24/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sony Corp (JP 086388)(paragraph citations to English translation) in view of Lin et al. (US 2011/0037051).
Sony Corp. disclose forming a plurality of semiconductor layers (12, 13, 14, 15) [0019, 0020] on a sapphire substrate (11)[0019], each of the plurality of semiconductor layers having a first surface on the sapphire substrate side and a second surface on the opposite side (fig. 1); joining the second surfaces of the plurality of semiconductor layers to a retention member(22) via an adhesive member(23)[0022] (fig. 6); peeling off the plurality of semiconductor layers from the sapphire substrate by irradiating the first surfaces of the plurality of semiconductor layers with laser light[0023]; and polishing the first surfaces of the plurality of semiconductor layers(fig. 7).
Sony fails to disclose wherein at least one semiconductor layer among the plurality of semiconductor layers includes a polishing indication part extending from the second surface toward the first surface, and wherein the polishing is executed until the polishing indication part is exposed to the polished surface.
Lin et al disclose wherein at least one semiconductor layer among the plurality of semiconductor layers includes a polishing indication part (trench/hole, 160, 200) extending from the second surface (top of 150) toward the first surface (bottom of 120) (fig. 2, and fig 5), and wherein the polishing is executed until the polishing indication part is exposed to the polished surface[0032](fig. 8).
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (using a trench for a polish stop), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable ( the trench/hole would indicate where the polish needed to stop).
Regarding claim 2, Lin et al. disclose the polishing indication part is a (filled) hole(/trench) (200) (fig. 5) formed from the second surface (top of 150) toward the first surface (bottom of 120), and wherein the polishing is executed until the hole is exposed to the polished surface (fig. 7-8) [0032].
Regarding claim 3, Sony Corp. disclose wherein the at least one semiconductor layer has a quadrangular shape (fig. 10) in a plane parallel to the first surface, and the combination of Sony Corp and Lin et al. disclose the hole (Lin et al. fig. 5) is formed in the vicinity (on same bonded wafer) of a corner part of the quadrangular shape (Sony fig. 10).
Regarding claim 4, the combination of Sony Corp. and Lin et al. disclose the polishing indication part includes a cutout part (hole/trench) (Lin et al. 200) (Lin et al. fig. 5) formed from the second surface toward the first surface, wherein a base part (Lin et al., 180) is formed on the first surface side of the cutout part, and wherein the polishing is executed until the cutout part is exposed to the polished surface (Lin et al., figs 7-8).
Regarding claim 6, Sony Corp. disclose wherein the at least one semiconductor layer includes a plurality of polishing indication parts(hole/trench) (200) (fig. 5) differing from each other in a distance of extension from the second surface.
Regarding claim 7, Sony Corp. disclose the polishing is executed until surface roughness becomes less than or equal to 10 nm [1.5nm, 0051].
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sony Corp (JP 086388)(paragraph citations to English translation) in view of Lin et al. (US 2011/0037051).
Sony Corp. disclose forming a plurality of semiconductor layers (12, 13, 14, 15) [0019, 0020] each of the plurality of semiconductor layers having a first surface (bottom of 12) and a second surface on the opposite side (top of 15) (fig. 1); a retention member (22) to which the second surfaces of the plurality of semiconductor layers are joined via an adhesive member (23)(fig.6), wherein at least one of the plurality of semiconductor layers includes a polishing indication part extending from the second surface toward the first surface.
Sony fails to disclose wherein at least one of the plurality of semiconductor layers includes a polishing indication part extending from the second surface toward the first surface.
Lin et al disclose wherein at least one of the plurality of semiconductor layers includes a polishing indication part (trench/hole, 160, 200) extending from the second surface(top of 150) toward the first surface(bottom of 120) (fig. 2, and fig 5)
.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (using a trench for a polish stop), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable ( the trench/hole would indicate where the polish needed to stop).
Regarding claim 11, Lin et al. disclose the polishing indication part is a hole (filled) hole(/trench) (200) (fig. 5) extending from the second surface(top of 150) toward the first surface (bottom of 120).
Regarding claim 12, the combination of Sony Corp and Lin et al. disclose the polishing indication part includes a cutout part (hole/trench) (Lin et al., 200) (Lin et al., fig. 5) extending from the second surface toward the first surface(Lin et al., fig. 5) , and wherein a base part (Lin et al., 180) is formed on the first surface side of the cutout part.
Allowable Subject Matter
Claims 5, 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the at least one semiconductor layer has a quadrangular shape in a plane parallel to the first surface, and wherein the cutout part is formed to cut away a corner part of the quadrangular shape (claim 5) wherein in the polishing, the retention member to which the plurality of semiconductor layers are joined via the adhesive member is held by a carrier of a polishing device, and wherein each of the adhesive member, the retention member and the carrier include a through hole at a position overlapping with the polishing indication part of the at least one semiconductor layer (claim 8) and forming supports on the plurality of semiconductor layers, wherein in the polishing, the supports are joined to the retention member via the adhesive member and the retention member is held by a carrier of a polishing device (claim 9).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
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/BRADLEY SMITH/Primary Examiner, Art Unit 2817