DETAILED ACTION
This Office action responds to Applicant’s arguments on 02/12/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The Applicant’s response on 02/12/2025 in reply to the non-final rejection mailed on 11/20/2025 has been entered. The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-6, 8-10, and 13-18. Claims 7, and 11-12 are withdrawn by the Applicant being drawn to non-elected species.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, and 3 are rejected under 35 U.S.C. 103 as being unpatentable by Iwamuro (US 2009/0114923) in view of Ujita (WO 2019/187789) [which designates the US and is deemed published under 122(b) per MPEP 2154.01(a). For ease of citation to figures and paragraph numbers, Examiner is using the corresponding application US 2021/0005742 (“Ujita”) which can trace its priority back to Mar. 27, 2018 per, inter alia, 35.U.S.C. § 122(b)].
Regarding claim 1, Iwamuro shows (see, e.g., Iwamuro: figs. 1 and 13) most aspects of a nitride semiconductor device 11, comprising:
A substrate 12
A first semiconductor layer 13/14 of a first conductivity type which is disposed above the substrate 12
A second semiconductor layer 15 of a second conductivity type which is disposed above the first semiconductor layer 13/14
A third semiconductor layer 16 which is disposed above the second semiconductor layer 15
A first opening 18 which penetrates through the third semiconductor layer 16 and the second semiconductor layer 15 to reach the first semiconductor layer 13/14
A groove 1 which is provided at an end portion of the nitride semiconductor device 11 and penetrates through the second semiconductor layer 15 (or 1) to reach the first semiconductor layer 13/14 (or 5)
A distance between a bottom of the first opening 18 and the substrate 12 is shorter than a distance between a bottom of the groove 1 and substrate 12
Iwamuro, however, fails (see, e.g., Iwamuro: figs. 1 and 13) to show a semiconductor multilayer having one portion disposed along an inner surface 22a/22b of the first opening 22 and an other portion disposed above the third semiconductor layer. Ujita, in a similar device to Iwamuro, shows (see, e.g., Ujita: fig. 2) a semiconductor multilayer 24/46/26 having one portion disposed along an inner surface 22a/22b of the first opening 22 and an other portion disposed above the third semiconductor layer 18/20
Ujita also shows (see, e.g., Ujita: fig. 2) that the semiconductor multilayer 24/46/26 contains an electron transport layer 24 and an electron supply layer 26 in that order from the side which the substrate 12 is located in order to supply and transport electrons to the channel for achieving higher outputs and breakdown voltages (see, e.g., Ujita: par. [0003]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the semiconductor multilayer of Ujitaa in the device of Iwamuro, in order to supply and transport electrons to the channel for achieving higher outputs and breakdown voltages.
Iwamuro in view of Ujita shows (see, e.g., Ujita: fig. 2) that:
The semiconductor multilayer 24/46/26 includes a channel region of the first conductivity type (see, e.g., Ujita: par. [0079])
A fourth semiconductor layer 28 of the second conductivity type which is disposed along an upper surface of the semiconductor multilayer 24/46/26 (see, e.g., Ujita: par. [0086])
A gate electrode 30 which is disposed above the fourth semiconductor layer 28
A source electrode 34 which is disposed away from the gate electrode 30
A drain electrode 36 which is disposed on a side of a lower surface of the substrate 12
Regarding claim 3, Iwamuro in view of Ujita shows (see, e.g., Ujita: fig. 2) that:
A second opening 32 which is provided away from the gate electrode 30 and penetrates through the semiconductor multilayer 24/46/26 and the third semiconductor layer 18/20 to reach the second semiconductor layer 16
The source electrode 34 is provided along an inner surface 32a/32b of the second opening 32
Claims 4, 6, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable by Iwamuro in view of Ujita in further view of Qingchun (CN 113130650 A).
Regarding claim 4, Iwamuro in view of Ujita shows (see, e.g., Ujita: fig. 2) to show that the first semiconductor layer 14 includes a plurality of layers each of which has a different impurity concentration. Qingchun, in a similar device to Iwamuro in view of Ujita, shows (see, e.g., Qingchun: fig. 1) a first semiconductor layer 1 that includes a plurality of layers 1a/1b each of which has a different impurity concentration (see, e.g., Qingchun: par. [0077]). Qingchun also shows that the setting with the first drift layer 1a overlapping the second drift layer 1b with different doping concentration can reduce the gate oxide electric field (see, e.g., Qingchun: par. [0077]).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first semiconductor layer with a plurality of layers each of which has a different impurity concentration of Qingchun in the device of Iwamuro in view of Ujita, in order to reduce the gate oxide electric field.
Iwamuro in view of Ujita in view of Qingchun shows (see, e.g., Qingchun: fig. 1) that the bottom of the first opening is located in an “nth”-layer from the uppermost layer 1b among the plurality of layers 1a/1b, where “n” is a natural number greater than or equal to two.
Regarding claim 6, Iwamuro in view of Ujita in view of Qingchun shows (see, e.g., Qingchun: fig. 1) that the plurality of layers 1a/1b are two layers.
Regarding claim 8, Iwamuro in view of Ujita in view of Qingchun shows (see, e.g., Qingchun: fig. 1) that the “nth” layer 1b has a highest impurity concentration among the plurality of layers 1b/1a (see, e.g., Qingchun: par. [0077]).
Regarding claim 9, Iwamuro in view of Ujita in view of Qingchun shows (see, e.g., Qingchun: fig. 1) that the uppermost layer 1a among the plurality of layers has a lower impurity concentration of the first conductivity type than the “nth” layer 1b (see, e.g., Qingchun: par. [0077]).
Allowable Subject Matter
Claims 2, 5, 10, 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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