DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park(USPGPUB DOCUMENT: 2022/0102358, hereinafter Park) in view of Tsutsumi (USPGPUB DOCUMENT: 2019/0096808, hereinafter Tsutsumi) and Manfrini (USPGPUB DOCUMENT: 2021/0242208, hereinafter Manfrini) and Hashemi (USPGPUB DOCUMENT: 2019/0326288, hereinafter Hashemi).
Re claim 11 Park discloses in Fig 2 a three-dimensional semiconductor structure, comprising: a semiconductor substrate(sub); a stack structure of insulating layers and semiconductor layers stacked alternately on the semiconductor substrate(sub), wherein the stack structure comprises, in a first direction(left/right), a channel region(region of CH), and a source region( region of SD1/SD2), and a drain region( region of SD1/SD2) on either side of the channel region(region of CH), wherein the first direction(left/right) is a direction parallel to a top surface of the semiconductor substrate(sub); a plurality of parallel first trenches (see Fig 2) extending in the first direction(left/right) and penetrating the stack structure in the source region( region of SD1/SD2) and the drain region( region of SD1/SD2) perpendicularly in the stack structure in the source region( region of SD1/SD2) and the drain region( region of SD1/SD2), wherein the semiconductor layers retained in the channel region(region of CH) serve as a plurality of channel body layers(layers of CH), wherein the channel body layers(layers of CH) extend in a second direction(up/down), each of the channel body layers(layers of CH) comprises a plurality of channel areas(CH) arranged in the second direction(up/down), and the second direction(up/down) is a direction having an included angle (angle between the second direction and first direction) with the first direction(left/right) and parallel to the top surface of the semiconductor substrate(sub);
Park do not disclose a through via in one end of the plurality of channel body layers(layers of CH) in the second direction(up/down), wherein the through via penetrates the ends perpendicularly and exposes a surface of the semiconductor substrate(sub); and a grounded conductive plug in the through via; wherein each of the semiconductor layers in the channel region is continuous in the second direction;
Tsutsumi discloses in Fig 24 a through via(116/114 of Tsutsumi) in one end of the plurality of channel body layers(layers of CH)[0152] in the second direction(up/down)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Tsutsumi to the teachings of Park in order to have contact via structures contacting word line electrically conductive strips [0003, Tsutsumi]. In doing so, a through via(116/114 of Tsutsumi) in one end of the plurality of channel body layers(layers of CH)[0152] in the second direction(up/down), wherein the through via penetrates the ends perpendicularly and exposes a surface of the semiconductor substrate(sub);
Park and Tsutsumi do not disclose a grounded conductive plug(86/142) in the through via; wherein each of the semiconductor layers in the channel region is continuous in the second direction;
Manfrini disclose a grounded conductive plug(Fig 1)[0002]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Manfrini to the teachings of Park in order to have different amounts of charge, which correspond to different data states [0002, Tsutsumi]. In doing so, a a grounded conductive plug(Fig 1) in the through via(116/114 of Tsutsumi).
Park and Tsutsumi and Manfrini do not disclose wherein each of the semiconductor layers in the channel region is continuous in the second direction;
Hashemi disclose wherein each of the semiconductor layers in the channel region(14P/14NS) is continuous in the second direction (left to right);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Hashemi to the teachings of Park in order to minimize memory loses in its stored data when power is lost [0002, Hashemi].
Re claim 12 Park, Tsutsumi, Manfrini and Hashemi disclose the three-dimensional semiconductor structure of claim 11, further comprising: a plurality of annular first openings located in the channel body layers(layers of CH), wherein the plurality of annular first openings are communicated with the plurality of parallel first trenches, and the channel body layers(layers of CH) retained between adjacent annular first openings in the second direction(up/down) serve as the channel areas(CH); a plurality of isolation structures filling the plurality of annular first openings; and word line structures extending in the second direction(up/down) on surfaces of the plurality of isolation structures and the plurality of channel areas(CH).
Re claim 13 Park, Tsutsumi, Manfrini and Hashemi disclose the three-dimensional semiconductor structure of claim 12, further comprising: drain areas in the semiconductor layers extending in the first direction(left/right) retained between adjacent first trenches in the drain region( region of SD1/SD2), and source areas in the semiconductor layers extending in the first direction(left/right) retained between adjacent first trenches in the source region( region of SD1/SD2), wherein each of the source areas is located in an extending direction of a corresponding one of the drain areas, and both each of the source areas and the corresponding one of the drain areas are connected with a corresponding one of the channel areas(CH).
Re claim 14 Park, Tsutsumi, Manfrini and Hashemi disclose the three-dimensional semiconductor structure of claim 13, wherein a doping type of the drain areas is a same as a doping type of the source areas and is opposite to a doping type of the channel areas(CH).
Re claim 15 Park, Tsutsumi, Manfrini and Hashemi disclose the three-dimensional semiconductor structure of claim 13, further comprising: second through vias each penetrating a plurality of drain areas in a vertical direction, and bit lines in the second through vias.
Re claim 16 Park, Tsutsumi, Manfrini and Hashemi disclose the three-dimensional semiconductor structure of claim 11, wherein the semiconductor substrate(sub) has a grounded end, and the grounded conductive plug(Fig 1)[0002 of Manfrini] is connected with the grounded end.
Re claim 17 Park, Tsutsumi, Manfrini and Hashemi disclose the three-dimensional semiconductor structure of claim 11, wherein a material of the grounded conductive plug(Fig 1)[0002 of Manfrini] is a doped semiconductor material or a metal.
Re claim 18 Park, Tsutsumi, Manfrini and Hashemi disclose the three-dimensional semiconductor structure of claim 12, wherein a depth of each of the plurality of annular first openings is 30%-45% of a thickness of each of the channel body layers(layers of CH), and a width of each of the plurality of annular first openings in the second direction(up/down) is 80%-95% of a width of each of the channel areas(CH) in the second direction(up/down).
Response to Arguments
Applicant’s arguments with respect to claim 11-18 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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