Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/09/2023 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-5 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claim limitation “far away” is indefinite, the meets and bounds of the claim cannot be determined. Examiner suggests replacing with “a second surface opposite said bottom surface of the groove”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 12-15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over ISHINO MASAKAZU et al., JP 2007194444 A and in further view of O'Brien; Richard J et al, US 20120101540 A1
Masakazu teaches:
a substrate (110, 10) and power supply pins (130;30); Figure 1 and conventional art Figure 7
a storage module (figure 1, 7);
wherein the storage module comprises a plurality of storage chips (121-125, 21-25) stacked in a first direction, wherein the first direction is parallel; (figure 1, 7);
power supply signal lines (121b, 122b, 123b, 124b, 125b) are provided in each of the storage chips, and at least one of the plurality of storage chips has a power supply wiring layer (125, 142) electrically connected to the power supply signal lines; (figure 1) and
conductive parts (140, 141) connected with the power supply wiring layer (125,142) and the power supply pins (130). Figure 1
Masakazu fails to teach:
a substrate having a groove and;
a storage module located in the groove parallel to a bottom surface of the groove.
O’Brien teaches:
a substrate (104) having a groove (figure 4) and;
a storage module (106) located in the groove (figure 4) parallel to a bottom surface of the groove. (figure 4) para 75
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of O’Brien, with the primary reference of Masakazu, because the storage device is enclosed within a cavity improving the scale of the device.
Masakazu teaches
2. The semiconductor structure of claim 1, wherein a side surface, far away from the bottom surface of the groove, of the power supply wiring layer (125, 142) is exposed by the at least one of the storage chips (121b-125b) and is connected to the conductive parts. (140, 141) Figure 1
12. The semiconductor structure of claim 1, wherein the power supply wiring layer comprises a plurality of power source wires and a plurality of ground wires; and the power supply signal lines comprise a plurality of power source signal lines and a plurality of ground signal lines; wherein the power source wires are electrically connected with the power source signal lines, and the ground wires are electrically connected with the ground signal lines; and
the power source wires and the ground wires are arranged alternately in a second direction, wherein the second direction is perpendicular to the first direction and parallel to the bottom surface of the groove.
In regards to claim 12, Masakazu is silent to the formation of ground wire. Examiner takes official notice that it is conventionally done in the art to prevent shorting.
13. The semiconductor structure of claim 1, further comprising:
a logic chip located between the bottom surface of the groove and the storage module;
wherein first wireless communication parts are provided in the storage chips; and
second wireless communication parts are provided in the logic chip;
wherein the first wireless communication parts are in wireless communication with the second wireless communication parts.
14. The semiconductor structure of claim 13, wherein an attach layer or a welding layer is further provided between the logic chip and the storage module.
In regards to claims 13 and 14, O’Brien teaches:
a die 108 (e.g., an integrated circuit die) is formed in the groove. (para 39)
And (para 048) connected to bonding pads 122 using a solder material such as gold-tin or tin-lead. Individually deposited portions of solder material that form connections between components of packaged devices may be referred to as solder bumps 124. Bonding pads 122 may be electrically interconnected by conductive traces. For example, the conductive traces may be deposited as one or more layers on interior surface 118, or may be embedded (e.g. etched and deposited) in planar substrate 102.
In regards to claim 15,
Masakazu teaches:
15. A method for manufacturing a semiconductor structure, comprising:
providing a substrate (110,10) and power supply pins (130, 30); Figure 1 and 7
providing a storage module (121-125, 21-25), wherein the storage module comprises a plurality of storage chips (121-125, 21-25) stacked in a first direction;
wherein power supply signal lines (121b, 122b, 123b, 124b, 125b) are provided in each of the storage chips, and at least one of the plurality of storage chips has a power supply wiring layer (125, 142) electrically connected to the power supply signal lines; and
connecting the power supply wiring layer (125, 142) with the power supply pins through conductive parts(140, 141). Figures 1 and 7
Masakazu fails to teach:
placing the storage module in the groove, and enabling the first direction to be parallel to a bottom surface of the groove.
O’Brien teaches:
placing the storage module (106) in the groove, and enabling the first direction to be parallel to a bottom surface of the groove. Figure 4
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of O’Brien, with the primary reference of Masakazu, because the storage device is enclosed within a cavity improving the scale of the device.
17. A semiconductor device, comprising:
Masakazu teaches:
a substrate (110,10) and power supply pins (130,30); Figure 1 and 7
a storage module (121-125);
wherein the storage module comprises a plurality of storage chips (121-125, 21-25) stacked in a first direction, wherein the first direction is parallel (figure 1 and 7);
power supply signal lines (121b, 122b, 123b, 124b, 125b) are provided in each of the storage chips (121-125), and at least one of the plurality of storage chips has a power supply wiring layer (125, 142) electrically connected to the power supply signal lines; and conductive parts connected with the power supply wiring layer and the power supply pins. (140, 141). Figures 1 and 7
Masakazu fails to teach:
a circuit board;
wherein the substrate is disposed on the circuit board;
a storage module located in the groove
wherein the first direction is parallel to a bottom surface of the groove;
O’Brien teaches:
a circuit board (para 123);
wherein the substrate (104) is disposed on the circuit board; (para 123);
a storage module (106) located in the groove, wherein the first direction is parallel to a bottom surface of the groove. Figure 4
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of O’Brien, with the primary reference of Masakazu, because the storage device is enclosed within a cavity improving the scale of the device.
Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masakazu and O’Brien as applied to claim 1 above, and further in view of CN 113056819 A.
Masakazu and O’Brien fails to teach:
6. The semiconductor structure of claim 1, wherein
at least one of the storage chips at both head and tail sides of the storage module has the power supply wiring layer;
conductive through holes are provided in the storage chips, wherein the conductive through holes are electrically connected with the power supply signal lines; and bonding layers are provided between adjacent storage chips, wherein the bonding layers are connected with the conductive through holes; and
the power supply signal lines of the plurality of storage chips are electrically connected with the power supply wiring layer through the conductive through holes and the bonding layers.
7. The semiconductor structure of claim 6, wherein the at least one of the storage chips at both the head and tail sides of the storage module has the power supply wiring layer; the power supply pins are located on a same side of the storage module and are disposed adjacent to the at least one of the storage chips with the power supply wiring layer; and
the power supply signal lines of all the storage chips are electrically connected with the power supply wiring layer.
8. The semiconductor structure of claim 6, wherein each of the storage chips at both the head and tail sides of the storage module has the power supply wiring layer;
the storage module comprises two chip groups arranged in the first direction, wherein each chip group comprises a plurality of storage chips; and
power supply signal lines of a same chip group are electrically connected to the power
supply wiring layer nearest to the chip group.
9. The semiconductor structure of claim 6, wherein each of the storage chips at both the head and tail sides of the storage module has a power supply wiring layer;
each of all the storage chips comprises a first power supply signal line group and a second power supply signal line group, wherein each of the first power supply signal line group and the second power supply signal line group comprises a plurality of power supply signal lines; and
first power supply signal line groups of all the storage chips are electrically connected to one power supply wiring layer; and second power supply signal line groups of all the storage chips are electrically connected to another power supply wiring layer.
CN 113056819 A discloses:
a semiconductor module and a manufacturing method therefor, and a semiconductor device including the semiconductor module (description, paragraphs 0041-0071, and figures 1-7 and 11). The semiconductor module comprises: a memory base 10, which has bumps 30 (equivalent to power supply pins); and a memory unit 20, which is located on the memory base 10, wherein the memory unit 20 comprises a plurality of memory chips 21 stacked in a first direction, which is parallel to a surface of the memory base 10, and the memory chips 21 are connected to an electrode layer 23 and a power circuit 12 by means of through electrodes 22. Also: a power supply signal line in each memory chip 21, and the electrode layer 23 constitutes a power supply wiring layer; and the power circuit 12 constitutes a conductive portion.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of ‘819 , with the primary references of Masakazu and O’Brien, because [it] provide[s] a semiconductor module capable of stably supplying power to a plurality of stacked memory chips, a DIMM module
17. A semiconductor device, comprising:
Masakazu teaches:
a substrate (110,10) and power supply pins (130,30); Figure 1 and 7
a storage module (121-125);
wherein the storage module comprises a plurality of storage chips (121-125,21-25) stacked in a first direction, wherein the first direction is parallel (figure 1 and 7);
power supply signal lines are provided in each of the storage chips, and at least one of the plurality of storage chips has a power supply wiring layer electrically connected to the power supply signal lines; and conductive parts connected with the power supply wiring layer and the power supply pins.
a circuit board (para 123); (O’Brien)
wherein the substrate is disposed on the circuit board;
Allowable Subject Matter
Claims 3-5,10-11, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art references fail to teach:
3. The semiconductor structure of claim 2, wherein the power supply wiring layer comprises a first wiring layer and a second wiring layer connected with each other, wherein the first wiring layer extends on a surface, perpendicular to the bottom surface of the groove, of the at least one of the storage chips, and the second wiring layer is located on a surface, far away from the bottom surface of the groove, of the at least one of the storage chips, and is connected to the conductive parts;
wherein a width of the second wiring layer in the first direction is larger than a width of the first wiring layer in the first direction.
10. The semiconductor structure of claim 1, wherein
each of the conductive parts comprises a perforation and a lead; wherein the perforation runs through the substrate and is connected between the lead and a corresponding one of the power supply pins; and the lead is connected to the power supply wiring layer.
16. The method for manufacturing the semiconductor structure of claim 15, wherein
providing the storage module comprises:
providing a plurality of storage chips;
forming a first power supply wiring layer on at least one of the plurality of storage chips;
and
after forming the first power supply wiring layer, stacking the plurality of storage chips;
and
the method further comprises: before packaging the storage module in the groove,
carrying out a first molding process on the storage module to form a first sealing layer surrounding the storage module, wherein the first sealing layer also exposes side surfaces, far away from the bottom surface of the groove, of the storage chips and the first power supply wiring layer; and
after the first molding process, forming a second power supply wiring layer on a side surface, far away from the bottom surface of the groove, the at least one of the storage chips, wherein the second power supply wiring layer is connected with the first power supply wiring layer;
wherein packaging the storage module in the groove comprises:
carrying out a second molding process to form a second sealing layer covering the second power supply wiring layer and at least part of a conductive part.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN 113056819 A discloses:
a semiconductor module and a manufacturing method therefor, and a semiconductor device including the semiconductor module (description, paragraphs 0041-0071, and figures 1-7 and 11). The semiconductor module comprises: a memory base 10, which has bumps 30 (equivalent to power supply pins); and a memory unit 20, which is located on the memory base 10, wherein the memory unit 20 comprises a plurality of memory chips 21 stacked in a first direction, which is parallel to a surface of the memory base 10, and the memory chips 21 are connected to an electrode layer 23 and a power circuit 12 by means of through electrodes 22. Also: a power supply signal line in each memory chip 21, and the electrode layer 23 constitutes a power supply wiring layer; and the power circuit 12 constitutes a conductive portion.
‘819 fails to teach:
the substrate having a groove, and a storage module being located in the groove.
CN 103208471 A teaches:
discloses a multi-chip package body (description, paragraphs 0047-0057, and figure 2), comprising a substrate 1, wherein the substrate 1 is provided with a groove 13, and a plurality of chips may be stacked in the groove 13.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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