DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on January 13, 2022. It is noted, however, that applicant has not filed a certified copy of the CN 202210038578.0 application as required by 37 CFR 1.55.
Claim Objections
Claim 16 is objected to because of the following informalities: the phrase, “is a same as a bulk material,” is grammatically incorrect. Appropriate correction is required.
The examiner believes that the above phrase should read is the same as a bulk material.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 14, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Surthi et al. (United States Patent Application Publication No. US 2013/0187279 A1, hereinafter “Surthi”).
In reference to claim 1, Surthi discloses a method which meets the claim. Fig. 1-9B of Surthi disclose a method for manufacturing a semiconductor structure which comprises providing a substrate (30). Fig. 9B shows that a bit line (50 – Surthi equates bit line with digit line – p. 1, paragraph 2) is formed that extends along a first direction (left to right) in the substrate (30). An active pillar (30, 34, 36) is formed on the bit line (50). A bottom surface of the active pillar (30, 34, 36) is in contact with the bit line (50). The active pillar is doped with an N-type element (32, 36 – p. 2, paragraph 21). An inversion region (34) is formed at a side surface of the active pillar (30, 34, 36) and is doped with a P-type element (p. 2, paragraph 21). A word line (70) is formed that extends along a second direction (into and out of the page of fig. 9B). It is understood that there is a dielectric layer in the form of a gate dielectric layer which is formed between the word line (70) and the inversion region (34) of the active pillar (30, 34, 36) and extends in the second direction (into and out of the page of fig. 9B). Thus the dielectric layer and the word line (70) are sequentially formed to extend in the second direction ((into and out of the page of fig. 9B) to wrap part of the inversion region (34) such that the dielectric layer is located between the word line (70) and the inversion region (34).
In reference to claim 14, Surthi discloses a device which meets the claim. Fig. 9B discloses a semiconductor structure which comprises a substrate (30) that has a bit line (50 – Surthi equates bit line with digit line – p. 1, paragraph 2) that extends along a first direction (left to right). An active pillar (30, 34, 36) is located on the bit line (50). A bottom surface of the active pillar (30, 34, 36) is in contact with the bit line (50). The active pillar is doped with an N-type element (32, 36 – p. 2, paragraph 21). An inversion region (34) is located on a side surface of the active pillar (30, 34, 36) and is doped with a P-type element (p. 2, paragraph 21). A word line (70) that extends along a second direction (into and out of the page). It is understood that there is a dielectric layer in the form of a gate dielectric layer which is between the word line (70) and the active pillar (30, 34, 36) and extends in the second direction. The dielectric layer and the word line (70) wrap part of the inversion region (34) and the dielectric layer is located between the word line (70) and the inversion region (34).
With regard to claim 16, fig. 1 shows that a bulk material of the inversion region (34) is the same as a bulk material of the active pillar (30, 34, 36).
In reference to claim 17, the bulk material of the inversion region (34) is silicon (p. 2, paragraph 21).
With regard to claim 18, the bulk material of the inversion region (34) is silicon (p. 2, paragraph 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Surthi in view of Gambino et al. (USPN 6,020,239, hereinafter “Gambino”).
In reference to claim 2, Surthi does not disclose that the inversion region (34 - fig. 1-9B) of the silicon pillar (30, 34, 36 - fig. 1-9B) is formed by a selective epitaxy growth process. However Gambino discloses that forming a pillar transistor by a selective epitaxy growth process leads to the benefit of device quality single crystal silicon (column 5, lines 66-67, column 6, lines 1-12). In view of Gambino, it would therefore be obvious to form the silicon pillar and thus the inversion region of Surthi by a selective epitaxy growth process.
With regard to claim 3, in the method of Surthi constructed in view of Gambino, the p-type inversion region (34 – fig. 1-9B of Surthi) is doped in-situ during the selective epitaxy growth process (column 5, lines 66-67, column 6, lines 1-12 – Gambino).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Surthi.
In reference to claim 4, fig. 3 of Surthi shows that part of the sidewall of the active pillar (30, 34, 36) is thinned along a thickness direction of the active pillar (30, 34, 36). Surthi does not explicitly disclose that the thinning process is performed before forming the inversion region (34). However it has been held to be prima facie obvious to reverse the order of the prior art process steps, Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959). Furthermore the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results, In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). Thus it would be obvious to perform the thinning process before forming the inversion region (34) in the method disclosed by Surthi.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Surthi in view of Hirai et al. (United States Patent Application Publication No. US 2019/0016126 A1, hereinafter “Hirai”).
In reference to claim 5, Surthi discloses that thinning is done by a wet etching process (p. 3, paragraph 25). Surthi does not explicitly disclose that an alkaline liquid is used. However Hirai discloses that a wet etching process which uses an alkaline liquid has the benefit of providing an etch with high precision (p. 10, paragraph 125). In view of Hirai, it would therefore be obvious to use an alkaline liquid in the wet etching process disclosed by Surthi.
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Surthi in view of Kouketsu et al. (United States Patent Application Publication No. US 2006/0244037 A1, hereinafter “Kouketsu”) and further in view of Lee (United States Patent Application Publication No. US 2001/0007365 A1, hereinafter “Lee”).
In reference to claim 13, fig. 1-9B of Surthi discloses that forming the bit line (50) comprises providing an initial substrate (30) having a channel (20) extending along the first direction. The bit line (50) fills the channel (20). Surthi does not disclose that the bit line is made by an epitaxially grown material. However Kouketsu discloses the formation of a bit line by an epitaxial growth process in order to attain a low resistance bit line (p. 2, paragraph 22). Lee discloses that low resistance bit lines are desirable in the art since they lead to high-speed memory devices (p. 1, paragraph 6). In view of Kouketsu and Lee, it would therefore be obvious to form the bit line by an epitaxial growth process.
In reference to claim 15, Surthi does not disclose that the bit line is formed of an n-type doped semiconductor material. However Kouketsu discloses the use of an n-type doped semiconductor bit line in order to attain a low resistance bit line (p. 4, paragraph 50). Lee discloses that low resistance bit lines are desirable in the art since they lead to high-speed memory devices (p. 1, paragraph 6). In view of Kouketsu and Lee, it would therefore be obvious to implement an n-type doped semiconductor bit line.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Surthi in view of Takaishi (United States Patent Application Publication No. US 2013/0307056 A1, hereinafter “Takaishi”).
In reference to claim 19, in fig. 1-9B of Surthi, the thickness of the inversion region (34) is the same as that of the pillar (30, 34, 36). Surthi does not disclose the exact thickness of the inversion region/pillar (34 – fig. 1-9B of Surthi) as that claimed by the applicant. However Takaishi discloses that the thickness/width of a pillar in a pillar transistor can be adjusted in order to tailor the threshold voltage (p. 1, paragraphs 29-30). Thus Takaishi makes it clear that the pillar thickness/width is a result effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the pillar thickness/width, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore claim 19 is not patentable over Surthi and Takaishi.
Allowable Subject Matter
Claims 6-12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a method for manufacturing a semiconductor structure which comprises providing a substrate; forming a bit line extending along a first direction in the substrate, forming an active pillar on the bit line such that a bottom surface of the active pillar is in contact with the bit line, with the active pillar being doped with an N-type element, forming an inversion region at a side surface of the active pillar such that the inversion region is doped with a P-type element, sequentially forming a dielectric layer and a word line extending along a second direction to wrap part of the inversion region such that the dielectric layer is located between the word line and the inversion region, thinning part of a sidewall of the active pillar along a thickness direction of the active pillar before forming the inversion region in combination with the specific deposition and processing of a first isolation layer, a sacrificial layer, and a second isolation layer before the thinning step as described by the applicant in claim 6. In the examiner’s opinion, it would also not be obvious to implement a semiconductor structure which comprises a substrate that has a bit line extending along a first direction, an active pillar located on the bit line such that a bottom surface of the active pillar is in contact with the bit line, with the active pillar being doped with an N-type element, an inversion region located on a side surface of the active pillar that is doped with a P-type element, a dielectric layer and a word line that extends along a second direction such that the dielectric layer and the word line wrap part of the inversion region, and the dielectric layer is located between the word line and the inversion region in combination with the specific height requirements of the inversion region and the height of the part of the inversion region wrapped by the dielectric layer and the word line as described by the applicant in claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893