DETAILED ACTION
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in DE on 3/21/2023. It is noted, however, that applicant has not filed a certified copy of the DE 102023202516.7 application as required by 37 CFR 1.55.
An attempt to retrieve the priority documents failed as identified in the notice filed 8/21/2024.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered.
Response to Amendment
Receipt is acknowledged of the amendment filed 6/20/2025. Claims 1-2, 4, 6, 8-14, 16-17 and 19-20 are pending. Claims 3, 5, 7, 15, and 18 were canceled. Claims 1, 8-9, 11, 13, 17, and 19-20 were amended.
The previous objection to the drawings is withdrawn in view of amended drawings filed 10/29/2025.
The Applicant’s response fails to address that the priority documents have not been received. Please provide a certified copy of the priority documents. The applicant has failed to address the issue.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4 and 6-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
It is the opinion of the examiner that Carvalho et al. US 2022/0231582 teaches all elements of claim 1, except “the layer-stacked PCB is ring or arc shaped” as recited in the amended claim and previously recited in claim 5 (now canceled), and it is the opinion of the examiner that it would be obvious to one of ordinary skill in the art to form Carvalho as ring or arc shaped in view of the prior art of record.
However, after further search and consideration, the examiner is rejecting the current claims over US 2024/0019273 (Kurz) which was cited by the applicant in PTO-892 filed 3/20/2025. Also see Figs. 1-3 of US 2023/0043918 (Welsch) cited in the IDS filed 12/26/2023.
See rejection of claims 1-4 and 6-20 provided below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, 6, 8-10, 12-14, 16-17, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0065610 (Heinemann) in view of US 2023/0043918 (Welsch) US 2015/0108357 (Rose).
Regarding claim 1, Heinemann teaches an inductive sensor assembly (scanning element 1 of Figs. 1-6; see [0002]) comprising:
a printed circuit board, PCB, arrangement comprising at least one layer-stacked PCB having at least one layer (a circuit board 1 comprises a stacked arrangement of layers A-F; see Fig. 4);
a sensor chip component element (electronic components 1.2; see Figs. 1, 3, 4; see [0035], [0052]); and
a coil system comprising one or more sensor coils corresponding to the sensor chip component element (first detector unit 1.11 comprises excitation and receiving tracks 1.111, 1.112, 1.113, 1.114, 1.115 formed in layers A, B; see Fig. 4; [0038], [0052]),
wherein:
the sensor chip component element and the coil system are respectively arranged on separate outer layers with at least one inner layer in between serving as a shielding layer (electronic components 1.2 are formed on a layer F and first detector unit 1.11 comprises excitation and receiving tracks 1.111, 1.112, 1.113, 1.114, 1.115 formed in layers A, B with shielding layer 1.13 formed in between at layer D; see Fig. 4);
the shielding layer is a copper shield (the shielding layers are relatively large-area copper layers; see [0043]);
a distance between the shielding layer and the coil system is based on a sensing signal strength requirement of the sensor to suppress noise while limiting attenuation of a voltage sensed by the inductive sensor assembly (the distance t between the shielding layer 1.13 and the first detecting unit is determined such that an impermissibly high measure of crosstalk signals is prevented but excessive damping of the excitation fields is avoided at the same time. In addition, the electromagnetic interference of detector units 1.11, 1.12 by electronic components 1.2 or from external sources is prevented; see [0048], [0054]); and
the layer-stacked PCB is ring or arc shaped (the PCB is ring-shaped; see Figs. 1-6).
Heinemann fails to teach the shielding layer is a fully filled copper shield configured to be used as digital ground.
Welsch teaches wherein the shielding layer is a fully filled copper shield (the shielding layers 12, 13 extend over the entire front side or the entire rear side of the circuit board to ensure maximum shielding; see [0007], [0012], [0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Welsh into Heinemann in order to gain the advantage of shielding layers manufactured as inner layers and separate high frequency areas, such as transmitter and receiver coils on front side from the electrical components on rear side 10 of circuit board, and it would have been obvious to one of ordinary skill in the art for the shield in Heinemann to be implemented as a fully filled copper shield.
Rose teaches a shield configured to be used as digital ground (a shield may be positioned over the portion of the circuit where digital signal processing occurs and may be connected to a digital ground; see [0018], [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Rose into Heinemann in order to gain the advantage of shielding layers connected to a digital ground to shield the digital circuitry and limit propagation between the digital portion and the analog portion of a mixed signal integrated circuit.
Regarding claim 13, Heinemann teaches a method for manufacturing an inductive sensor assembly (see scanning element 1 of Figs. 1-6; see [0002]), the method comprising:
providing a printed circuit board, PCB, arrangement comprising at least one layer-stacked PCB, each having at least one layer (a circuit board 1 comprises a stacked arrangement of layers A-F; see Fig. 4);
providing a sensor chip component element (electronic components 1.2; see Figs. 1, 3, 4; see [0035], [0052]);
providing a coil system comprising one or more sensor coils corresponding to the sensor chip component element (first detector unit 1.11 comprises excitation and receiving tracks 1.111, 1.112, 1.113, 1.114, 1.115 formed in layers A, B; see Fig. 4; [0038], [0052]);
arranging the sensor chip component element and the coil system, respectively, on separate outer layers with at least one inner layer in between serving as a shielding layer, wherein, the shielding layer is a copper shield (electronic components 1.2 are formed on a layer F and first detector unit 1.11 comprises excitation and receiving tracks 1.111, 1.112, 1.113, 1.114, 1.115 formed in layers A, B with shielding layer 1.13 formed in between at layer D; see Fig. 4);
arranging a distance between the shielding layer and the coil system to be based on a sensing signal strength requirement of the sensor to suppress noise while limiting attenuation of a voltage sensed by the inductive sensor assembly (the distance t between the shielding layer 1.13 and the first detecting unit is determined such that an impermissibly high measure of crosstalk signals is prevented but excessive damping of the excitation fields is avoided at the same time. In addition, the electromagnetic interference of detector units 1.11, 1.12 by electronic components 1.2 or from external sources is prevented; see [0048], [0054]),
wherein the layer-stacked PCB is ring or arc shaped (the PCB is ring-shaped; see Figs. 1-6).
Heinemann fails to teach wherein, the shielding layer is a fully filled copper shield configured to be used as digital ground.
Welsh teaches wherein the shielding layer is a fully filled copper shield (the shielding layers 12, 13 extend over the entire front side or the entire rear side of the circuit board to ensure maximum shielding; see [0007], [0012], [0023]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Welsh into Heinemann in order to gain the advantage of shielding layers manufactured as inner layers and separate high frequency areas, such as transmitter and receiver coils on front side from the electrical components on rear side 10 of circuit board, and it would have been obvious to one of ordinary skill in the art for the shield in Heinemann to be implemented as a fully filled copper shield.
Rose teaches a shield configured to be used as digital ground (a shield may be positioned over the portion of the circuit where digital signal processing occurs and may be connected to a digital ground; see [0018], [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Rose into Heinemann in order to gain the advantage of shielding layers connected to a digital ground to shield the digital circuitry and limit propagation between the digital portion and the analog portion of a mixed signal integrated circuit.
Regarding claims 2 and 14, Heinemann teaches wherein the sensor chip component element is arranged on a component placement side of the PCB arrangement; and the coil system is arranged on a coil placement side of the PCB arrangement away from the sensor chip component element (see rejection of claim 1 and Fig. 4).
Regarding claim 4, Heinemann teaches wherein the sensor chip component element and the coil system are arranged on separate layers of the layer-stacked PCB (electronic components 1.2 are formed on a layer F and first detector unit 1.11 comprises excitation and receiving tracks 1.111, 1.112, 1.113, 1.114, 1.115 formed in layers A, B with shielding layer 1.13 formed in between at layer D; see Fig. 4).
Regarding claims 6 and 16, Heinamann teaches wherein: the inductive sensor assembly further comprises at least one conductive and rotatory sensor target; the sensor target is arranged on the same side of the PCB arrangement as the coil system, away from the sensor chip component element (the scanning element 1 comprises a first scale element 2 comprising conductive targets 2.11, 2.21 and the first scale element 2 is arranged on the same side of the PCB 1 as the first detective unit 1.11; see Figs. 1-5; see [0034] and [0051]); and the coil system comprises at least one transmit coil and at least one receive coil arranged for determining positions of the sensor target during rotation (the first detector unit 1.11 comprises receiving coils 1.112, 1.114 and excitation coils 1.111, 1.113, 1.115 for determining a position of the target; see Figs. 1-4; see [0034]).
Regarding claims 8 and 17, Heinemann teaches wherein: the layer-stacked PCB comprises four layers which are arranged as, in a thickness direction, a top outer layer, a top inner layer, a bottom inner layer, and a bottom outer layer; the sensor chip component element is arranged on the top outer layer; and the sensor coils of the coil system are arranged on the bottom inner layer and the bottom outer layer (scanning element 1 comprises layers A, B, E, F with the electronic components 1.2 arranged on the top outer layer f and the coils of detector unit 1.11 are arranged on the bottom outer layer A and the bottom inner layer B; see Fig. 4).
Regarding claims 9 and 19, Heinemann teaches wherein: the PCB arrangement comprises two separate layer-stacked PCBs stacked together each having at least one layer; and the sensor chip component element and the coil system are respectively arranged on the two separate layer-stacked PCBs, away from each other (the arrangement comprises layers A-C stacked together and layers D-F staged together as claimed; see Fig. 4).
Regarding claim 10, Heinemann teaches wherein: the sensor coils of the coil system are arranged on a first PCB; the sensor chip component element is arranged on a second PCB; and the second PCB further comprises a shielding layer that is arranged, in a thickness direction, between the sensor chip component element and the coil system (the arrangement comprises coil elements 1.111-1.115 arranged in layers A-C and electronic components 1.2 arranged on layers D-F with shield 1.13 arranged between; see Fig. 4).
Regarding claim 12, Heinemann teaches an inductive position sensor comprising the inductive sensor assembly according to claim 1 (see rejection of claim 1).
Claim(s) 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0065610 (Heinemann) in view of US 2023/0043918 (Welsch) US 2015/0108357 (Rose).
Regarding claims 11 and 20, Heinemann fails to teach wherein the PCB arrangement further comprises a conducting shield comprising a ferrite sheet, arranged between the two separate layer-stacked PCBs.
Elliott teaches wherein the PCB arrangement further comprises a conducting shield comprising a ferrite sheet, arranged between the two separate layer-stacked PCBs (a sensor package 10 is made from printed circuit boards and a ferrite layer is arranged between coils 32, 36, 22 and a layer comprising the signal processor 14 and a shield in the form of an integrated capacitor 16; see [0007], [0026], [0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the features of Elliott into Heinemann in order to gain the advantage of ferrite shields which is particularly advantageous as it is a high permeability material at nominal operating frequency of sensors and functions as an effective equivalent air gap and allows the size of the coils to be significantly reduced relative to conventional inductive sensors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN LEE YENINAS whose telephone number is (571)270-0372. The examiner can normally be reached M - F 10 - 6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN L YENINAS/Primary Examiner, Art Unit 2858
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