Prosecution Insights
Last updated: April 19, 2026
Application No. 18/446,723

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE

Non-Final OA §103
Filed
Aug 09, 2023
Examiner
CRITE, ANTONIO B
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Enkris Semiconductor (Wuxi) Ltd.
OA Round
2 (Non-Final)
81%
Grant Probability
Favorable
2-3
OA Rounds
2y 5m
To Grant
69%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
351 granted / 435 resolved
+12.7% vs TC avg
Minimal -12% lift
Without
With
+-11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
31 currently pending
Career history
466
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
51.5%
+11.5% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
20.1%
-19.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 435 resolved cases

Office Action

§103
DETAILED ACTION This Action is responsive to the communication filed on 12/29/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Allowable Subject Matter The indicated allowability of dependent claim 7 is withdrawn in view of reference(s) to Jean (US 2023/0275183). Rejections based on the cited reference(s) follow. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3-4, 6, 8-9, 11-13, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jean (US 2023/0275183), in view of Song (US 2022/0231203). Regarding claim 1, Jean (see, e.g., FIG. 4C) discloses a semiconductor structure, comprising: a light-emitting structure 120U (left), 120U (middle), 120U (right) (Para 0061); a light control layer 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)], 174 (left), 174 (middle), 174 (right) disposed on a side of the light-emitting structure 120U (left), 120U (middle), 120U (right), wherein the light control layer 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)], 174 (left), 174 (middle), 174 (right) comprises a plurality of light control regions e.g., region of 174 (left), 174 (middle), 174 (right) regularly arranged and a substrate structure 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)] located between the plurality of light control regions e.g., region of 174 (left), 174 (middle), 174 (right) (Para 0055, Para 0075, Para 0079-Para 0082), wherein the plurality of light control regions e.g., region of 174 (left), 174 (middle), 174 (right) comprise a wavelength conversion structure 174 (left), 174 (middle), 174 (right), and the wavelength conversion structure 174 (left), 174 (middle), 174 (right) comprises a quantum dot e.g., quantum dots within 174 (Para 0080-Para 0082), and the plurality of light control region e.g., region of 174 (left), 174 (middle), 174 (right) comprise a first color light region e.g., region of 174 (left), a second color light region e.g., 174 (middle), and a third color light region e.g., 174 (right) horizontally spaced (Para 0055, Para 0075, Para 0079-Para 0082). Although Jean shows substantial features of the claimed invention, Jean fails to expressly teach that the wavelength conversion structure comprises a porous structure adsorbed with the quantum dot. Song (see, e.g., FIG. 1C) teaches wavelength conversion structure 130 comprises a porous structure 120 adsorbed with the quantum dots 131, 133, 135 for the purpose of achieving a mixed color emission (Para 0055, Para 0058-Para 0059). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wavelength conversion structure of Jean to comprise wavelength conversion structure that comprises a porous structure adsorbed with the quantum dot as described by Song for the purpose of achieving a mixed color emission from a light emitting device (Para 0059, Para 0060). Regarding claim 3, the combination of Jean (see, e.g., FIG. 4C) / Song (see, e.g., FIG. 1C) teaches that the porous structure 120 (as taught by Song) has a hole 123 (as taught by Song) capable of adsorbing the quantum dot 131, 133, 135 (as taught by Song), the hole 123 (as taught by Song) is columnar in shape, and an angle between the hole 123 (as taught by Song) and a plane where the substrate structure 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)] (as taught by Jean) is located ranges from 60° to 120° (Para 0054-Para 0055). Regarding claim 4, Jean (see, e.g., FIG. 4C) teaches that each of the plurality of light control regions e.g., region of 174 (left), 174 (middle), 174 (right) further comprises an opening 160OP penetrating through the each of the plurality of light control regions e.g., region of 174 (left), 174 (middle), 174 (right), and the opening 160OP and the wavelength conversion structure 174 (left), 174 (middle, 174 (right) are arranged horizontally to be separated by the substrate structure 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)] (Para 0079). Regarding claim 6, Jean (see, e.g., FIG. 4C) teaches a thickness of the light control layer 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)], 174 (left), 174 (middle), 174 (right) is less than or equal to 50 µm (Para 0060). Regarding claim 8, Jean (see, e.g., FIG. 4C) teaches the semiconductor structure according to claim 1, wherein a hole proportion of the first color light region e.g., region of 174 (left), a hole proportion of the second color light region e.g., region of 174 (middle), and a hole proportion of the third color light region e.g., region of 174 (right) are the same or different. Regarding claim 9, Jean (see, e.g., FIG. 4C) teaches that a side wall of the plurality of light control regions e.g., region of 174 (left), 174 (middle), 174 (right) is provided with a light reflection layer 172 (Para 0078). Regarding claim 11, Jean (see, e.g., FIG. 4C) teaches that the light-emitting structure 120U (left), 120U (middle), 120U (right) comprises: a first semiconductor layer 14, an active layer 15, a second semiconductor layer 16, and at least one set of a first electrode 142A and a second electrode 142B (Para 0063); the first electrode 142A is connected to the first semiconductor layer 14 and blocked with the second semiconductor layer 16 and the active layer 15 through an insulating material 132 (Para 0063, Para 0064); and the second electrode 142B is connected to the second semiconductor layer 16 and blocked with the first electrode 142A through an insulating material 132 (Para 0063, Para 0064). Regarding claim 12, Jean (see, e.g., FIG. 4C) teaches that the light-emitting structure 120U (left), 120U (middle), 120U (right) comprises a plurality of light-emitting units 120U (left), 120U (middle), 120U (right), an insulation structure 132 is arranged between two adjacent light-emitting units 120U (left), 120U (middle), 120U (right), and a thickness of the insulation structure 132 is less than or equal to a thickness of the light-emitting structure 120U (left), 120U (middle), 120U (right) (Para 0063-Para 0065). Regarding claim 13, Jean (see, e.g., FIG. 7A-FIG. 7H) discloses a manufacturing method for a semiconductor structure, comprising: providing a silicon substrate 110 (Para 0098); forming a light-emitting structure 120U (left), 120U (middle), 120U (right) on a side of the silicon substrate 110 (Para 0099); thinning the silicon substrate 110 from the other side, away from the light-emitting structure 120U (left), 120U (middle), 120U (right), of the silicon substrate 110 (Para 0107); and forming a plurality of light control regions e.g., regions of 174 (left), 174 (middle), 174 (right) regularly arranged in a remaining silicon substrate 110, 160 to form a light control layer 160, 174 (left), 174 (right), the light control layer 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)], 174 (left), 174 (middle), 174 (right) further comprising a substrate structure 160 [between 174 (middle) and 174 (right)], 160 [between 174 (left) and 174 (middle)], 160 (right of 174 (right)] arranged between the plurality of light control regions e.g., regions of 174 (left), 174 (middle), 174 (right) (Para 0108, Para 0113); wherein the plurality of light control regions e.g., regions of 174 (left), 174 (middle), 174 (right) comprise a wavelength conversion structure e.g., regions of 174 (left), 174 (middle), 174 (right), and the wavelength conversion structure e.g., regions of 174 (left), 174 (middle), 174 (right) comprises a quantum dot (Para 0080-Para 0082) , and the plurality of light control region e.g., region of 174 (left), 174 (middle), 174 (right) comprise a first color light region e.g., region of 174 (left), a second color light region e.g., 174 (middle), and a third color light region e.g., 174 (right) horizontally spaced (Para 0055, Para 0075, Para 0079-Para 0082), Although Jean shows substantial features of the claimed invention, Jean fails to expressly teach that the wavelength conversion structure comprises a porous structure adsorbed with the quantum dot. Song (see, e.g., FIG. 1C) teaches wavelength conversion structure 130 comprises a porous structure 120 adsorbed with the quantum dots 131, 133, 135 for the purpose of achieving a mixed color emission (Para 0055, Para 0058-Para 0059). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wavelength conversion structure of Jean to comprise wavelength conversion structure comprises a porous structure adsorbed with the quantum dot as described by Song for the purpose of achieving a mixed color emission from a light emitting device (Para 0059, Para 0060). Regarding claim 16, the combination of Jean (see, e.g., FIG. 7A-FIG. 7H) / Song (see, e.g., FIG. 1C) teaches the manufacturing method for a semiconductor structure according to claim 13, wherein the providing a silicon substrate 110 (as taught by Jean) further comprises: preparing a hole on a side 160OP (as taught by Jean), away from a growth surface e.g., surface of LS adjacent to BS, of the silicon substrate 110 (as taught by Jean) to form a plurality of porous structures 120 (as taught by Song) regularly arranged (Jean: Para 0037, Para 0038, Para 0075; Song: Para 0055, Para 0058-Para 0059). Regarding claim 18, the combination of Jean (see, e.g., FIG. 7A-FIG. 7H) / Song (see, e.g., FIG. 1C) teaches the manufacturing method for a semiconductor structure according to claim 13, wherein the thinning the silicon substrate 110 (as taught by Jean) from the other side, away from the light-emitting structure LS (as taught by Jean), of the silicon substrate 110 (as taught by Jean) further comprises: preparing holes 160OP (as taught by Jean) on a side, away from the light-emitting structure LS (as taught by Jean), of the silicon substrate 110 (as taught by Jean) thinned to form the plurality of porous structures 120 (as taught by Song) regularly arranged (Jean: Para 0037, Para 0038, Para 0075; Song: Para 0055, Para 0058-Para 0059). Regarding claim 19, Jean (see, e.g., FIG. 7A-FIG. 7H) teaches that the forming a light-emitting structure 120U (left), 120U (middle), 120U (right) on a side of the silicon substrate 110 further comprises: growing a first semiconductor layer 14, an active layer 15, and a second semiconductor layer 16 on a side of the silicon substrate 110 sequentially (Para 0089, Para 0095); forming at least one filling groove E on a side, away from the silicon substrate 110, of the second semiconductor layer 16, wherein each of the at least one filling groove E completely penetrates the second semiconductor layer 16, the active layer 15, and partially penetrates the first semiconductor layer 14 (Para 0100); preparing a first electrode 142A in the at least one filling groove E, wherein the first electrode 142A is insulated and blocked with the second semiconductor layer 16 and the active layer 15, and the first electrode 142A is connected to the first semiconductor layer 14 (Para 0063, Para 0064, Para 0102); and preparing a second electrode 142B on a side, away from the active layer 15, of the second semiconductor layer 16, wherein the second electrode 142B is insulated and blocked with the first electrode 142A (Para 0063, Para 0064, Para 0103). Regarding claim 20, Jean (see, e.g., FIG. 7A-FIG. 7H) teaches that the light-emitting structure 120U (left), 120U (middle), 120U (right) comprises a plurality of light-emitting units 120U (left), 120U (middle), 120U (right), and after the growing a first semiconductor layer 14, an active layer 15, and a second semiconductor layer 16 on a side of the silicon substrate 110 sequentially, the manufacturing method for a semiconductor structure further comprises: forming an insulation structure 132 between two adjacent light emitting units 120U (left), 120U (middle), 120U (right) on a side, away from the silicon substrate 110, of the second semiconductor layer 16, wherein a thickness of the insulation structure 132 is less than or equal to a thickness of the light-emitting structure 120U (left), 120U (middle), 120U (right) (Para 0063, Para 0064). Allowable Subject Matter Claims 2, 5, 10, 14-15, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claims 1 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Aug 09, 2023
Application Filed
Sep 27, 2025
Non-Final Rejection — §103
Dec 29, 2025
Response Filed
Feb 23, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
81%
Grant Probability
69%
With Interview (-11.9%)
2y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 435 resolved cases by this examiner. Grant probability derived from career allow rate.

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