DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-6, 8-13 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Kim et al., US 2023/0065378 A1.
Claim 1. Kim et al., disclose a semiconductor package (such as the one in fig. 7B) comprising:
-a front side redistribution layer (top surface of item 100);
-a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die (item 210) and a second semiconductor chip die (item 220) having through-silicon vias (TSVs) (item 215), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs (as [0031] disclose that first redistribution patterns 130 may include metal, such as copper. The phrase “electrically connected to the first redistribution substrate 100” may include the meaning of “electrically connected to one of the first redistribution patterns 130”);
-a printed circuit board (item 700, fig. 7B) on the front side redistribution layer and surrounding the 3D IC structure;
-a molding material (items 410/420/740) on the front side redistribution layer and at least partially encapsulating the 3D IC structure and the printed circuit board;
-and a back side redistribution layer (item 600) on the molding material.
Claim 2. Kim et al., disclose the semiconductor package of claim 1, further comprising: connection members between the first semiconductor chip die and the second semiconductor chip die, wherein the connection members include micro bumps (items 510/521, fig. 7B).
Claim 3. Kim et al., disclose the semiconductor package of claim 1, wherein: the first semiconductor chip die includes a plurality of first bonding pads (item 211/212) and a first insulating layer (item 101), and the second semiconductor chip die includes a plurality of second bonding pads (item 221) and a second insulating layer (item 601).
Claims 4-6. Kim et al., disclose the semiconductor package of claim 3, wherein the plurality of first bonding pads are directly bonded to the plurality of second bonding pads (this limitation would read through [0036] wherein is disclosed each of the first redistribution pads 150 may include a body part 151 and a bonding part 152), wherein the plurality of first bonding pads and the plurality of second bonding pads include copper (Cu) (this limitation would read through [0036] wherein is disclosed the body part 151 may include metal, such as copper).
Claim 8. Kim et al., disclose the semiconductor package of claim 1, wherein: the second semiconductor chip die includes a plurality of connection terminals, the front side redistribution layer includes a plurality of redistribution vias at an uppermost level thereof, and the plurality of redistribution vias are directly bonded to the plurality of connection terminals (this limitation would read through [0035] wherein is disclosed the first redistribution pads 150 may be laterally spaced apart from each other. The first redistribution pads 150 may be disposed on and coupled to the first redistribution patterns 130. Each of the first redistribution pads 150 may be coupled to a corresponding under-bump pattern 120 through the lower redistribution pattern and the upper redistribution pattern).
Claim 9. Kim et al., disclose the semiconductor package of claim 1, wherein the molding material includes an epoxy molding compound (EMC) (this limitation would read through [0042] wherein is disclosed the under-fill layer may include a dielectric polymer, such as an epoxy polymer).
Claim 10. Kim et al., disclose the semiconductor package of claim 1, wherein the printed circuit board includes an embedded trace substrate (ETS) (this limitation would read through [0127] wherein is disclosed the upper substrate 700 may be a printed circuit board (PCB) or a redistribution layer).
Claim 11. Kim et al., disclose the semiconductor package of claim 1, wherein the 3D IC structure includes a system-on-chip (SOC) (this limitation would read through [0164] wherein is disclosed the upper semiconductor chip may be disposed on the lower semiconductor chip).
Claim 12. Kim et al., disclose a semiconductor package (such as the one in fig. 7B) comprising:
-a front side redistribution layer (item 100) including a plurality of first redistribution vias (items 311/312/320);
-a three-dimensional integrated circuit (3D IC) structure on the front side redistribution layer, the 3D IC structure including a first semiconductor chip die (item 210) and a second semiconductor chip die having through-silicon vias (TSVs) (item 215), the first semiconductor chip die on the second semiconductor chip die and electrically coupled with the front side redistribution layer by the TSVs (as seen in the structure of fig. 7B);
-a printed circuit board (item 700, fig. 7B) on the front side redistribution layer and surrounding the 3D IC structure;
-a plurality of conductive fillers on the printed circuit board (this limitation would read through [0065] wherein is disclosed the first fillers may be provided in the first dielectric polymer. The first fillers may include an inorganic material, such as silica);
-a molding material (items 410/420/740) on the front side redistribution layer and at least partially encapsulating the 3D IC structure, the printed circuit board, and the plurality of conductive fillers;
-a back side redistribution layer (item 600) on the molding material and including a plurality of second redistribution vias;
-and a third semiconductor chip die (item 720) on the back side redistribution layer.
Claim 13. Kim et al., disclose the semiconductor package of claim 12, wherein: a width of an uppermost part of each first redistribution via of the plurality of first redistribution vias is smaller than a width of a lowermost part of each first redistribution via of the plurality of first redistribution vias, (this limitation would read through [0044] wherein is disclosed the upper semiconductor chip may be disposed on the lower semiconductor chip) and a width of an uppermost part of each second redistribution via of the plurality of second redistribution vias is larger than a width of a lowermost part of each second redistribution via of the plurality of second redistribution vias (this limitation would read through [0048] wherein is disclosed the second width W12 may be greater than the width W1 of the through vias 215. The second width W12 may be the same as the first width W11).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
5. Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 2023/0065378 A1, in view of Yu et al., US 2015/0303174 A1.
Claim 7. Kim et al., disclose the semiconductor package of claim 3, wherein the first insulating layer is directly bonded to the second insulating layer (this limitation would read through [0067] of Kim, wherein is disclosed the upper molding layer 420 may be in direct contact with the top surface of the lower molding layer 410).
Kim appears to not specify that the first insulating layer and the second insulating layer include silicon oxide.
However, in a similar package, [0033] of Yu et al., disclose the ILD and IMDs may be made of, for example, silicon oxide, SiCOH, and the like.
Therefore, it would have been within the skill of one of ordinary skill in the art before the effective filling date of the invention to form the first insulating layer and the second insulating layer include silicon oxide, in order to provide crucial electrical insulation, surface passivation, and structural support, enabling functions like transistor isolation (especially in SOI), reducing leakage currents for faster, lower-power devices, and acting as protective masks during fabrication. These layers are vital for preventing unwanted current flow, improving device performance, and creating the complex structures needed in modern microelectronics.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899