Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (device), Species B in the reply filed on 10/14/25 is acknowledged.
Claims 7-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II (method)/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/14/25.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 2 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US PGPub 2022/0093629).
Claim 1: Kim teaches (Fig. 1, 7) a vertical nonvolatile memory device comprising: a peripheral circuit portion (PS) including a memory cell driving circuit and connection wiring [0059]; a first hydrogen diffusion barrier layer (53) above the peripheral circuit portion; a first insulating layer (100) above the first hydrogen diffusion barrier layer; a common source line layer (CST) above the first insulating layer; a second hydrogen diffusion barrier layer (ILD) above the first insulating layer; and a memory cell stack structure (ST) above the common source line layer and the second hydrogen diffusion barrier layer.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang et al. (US PGPub 2023/0328985) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim 1: Kang teaches (Fig. 1A) vertical nonvolatile memory device comprising: a peripheral circuit portion (PERI) including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer (250) above the peripheral circuit portion; a first insulating layer (294/298) above the first hydrogen diffusion barrier layer; a common source line layer (102) [0053] above the first insulating layer; a second hydrogen diffusion barrier layer (260/105i) above the first insulating layer; and a memory cell stack (Cell, 120,130) structure above the common source line layer and the second hydrogen diffusion barrier layer.
Claim 2: Kang teaches (Fig. 1A) the second hydrogen diffusion barrier layer (105i) covers sidewalls of the common source line layer (102) and an exposed portion of the first insulating layer (298), and the exposed portion of the first insulating layer is not covered by the common source line layer such that the exposed portion of the first insulating layer is exposed by the common source line layer.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US PGPub 2023/0389322) .
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim 1: Lee teaches (Fig. 1A) vertical nonvolatile memory device comprising: a peripheral circuit portion (PERI) including a memory cell driving circuit and connection wiring; a first hydrogen diffusion barrier layer (295) above the peripheral circuit portion; a first insulating layer (296/298) above the first hydrogen diffusion barrier layer; a common source line layer (102,104) above the first insulating layer; a second hydrogen diffusion barrier layer (297/105i) above the first insulating layer; and a memory cell stack (CELL, 120,130) structure above the common source line layer and the second hydrogen diffusion barrier layer.
Claim 2: Lee teaches (Fig. 1A) the second hydrogen diffusion barrier layer (105i) covers sidewalls of the common source line layer (102) and an exposed portion of the first insulating layer (298), and the exposed portion of the first insulating layer is not covered by the common source line layer such that the exposed portion of the first insulating layer is exposed by the common source line layer.
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach the limitations of claim 3. Claims 4-6 depend from claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814