DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al (US Publication no. 2022/0114320) in view of Chen et al (US Publication No. 2019/0155984) and Liebmann et al (US Publication No. 2021/0118798).
Regarding claim 1, Yu discloses a semiconductor integrated circuit device comprising a plurality of standard cells each having a fin field effect transistor (FET) Fig 3 and Fig 5 ¶0039,wherein a plurality of fins constituting the fin FET extend in a first direction and placed on ones of spacing equally spaced in a second direction vertical to the first direction Fig 3 and Fig 5 ¶0040-0041,the plurality of standard cells include a first standard cell Fig 3, C11 and a second standard cell Fig 3, C12 larger in size in the second direction than the first standard cell Fig 3 ¶0040, the FET includes a gate Fig 3;
the first standard cell includes a first buried power line Fig 5, PL3c extending in the first direction, the second standard cell includes a second buried power line Fig 5, PL1c extending in the first direction, the second buried power line being larger in size in the second direction than the first buried power line ¶0051-0052 Fig 3, and a center position of each of the first and second buried power lines in the second direction is on one of the spacing or at a center position between adjacent ones of the spacing Fig 3, Fig 5 and Fig 7 ¶0053.Although Yu does not explicitly discloses a virtual grid lines, Yu discloses a spacing structure similar to a gid lines. While Chen discloses a virtual grid lines ¶0044-0046, 0049. Yu and Chen are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor. It would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the spacing structure of Yu and incorporate a similar alignment structure to improve device placement. Yu and Chen discloses all the limitations but silent on the arrangement of the power line.
Whereas Liebmann discloses the FET includes a gate Fig 5; the first power line Fig 5, 292-294 being laid below the gate interconnect Fig 5 and the gate interconnects being formed in the same layer as the gate Fig 5, the second power line being laid below the gate interconnects Fig 5, 292-294. Yu and Liebmann are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yu because they are from the same field of endeavor. It would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the power rail arrangement of Yu and incorporate the teachings of Liebermann to improve device connectivity.
Regarding claim 2, Yu discloses wherein the first standard cell includes a first fin FET having N (N is an integer equal to or greater than 1) fin or fins, and the second standard cell includes a second fin FET having M (M is an integer greater than N) fins Fig 3 and Fig 5.
Regarding claim 3, Yu discloses wherein the first standard cell includes a first local interconnect ¶0081 extending in the second direction and connected to the first buried power line through a first via Fig 3 and Fig 4A-4D,the second standard cell includes a second local interconnect extending in the second direction and connected to the second buried power line through a second via, and the second via is larger in size than the first via, or the number of second vias is larger than the number of first vias Fig 3 and Fig 5.
Regarding claim 4, Yu discloses wherein the first and second standard cells achieve the same circuit function ¶0026-0030.
Regarding claim 5, Yu discloses wherein the plurality of standard cells include a third standard cell larger in size in the second direction than the second standard cell, and the third standard cell includes a third buried power line extending in the first direction, the third buried power line being larger in size in the second direction than the second buried power line ¶0071-0076.Whilef Liebermann discloses the third power line being laid below the gate interconnects Fig 5.
Regarding claim 6, Yu discloses wherein the first standard cell includes a first fin FET having N (N is an integer equal to or greater than 1) fin or fins, the second standard cell includes a second fin FET having M (M is an integer greater than N) fins, and the third standard cell includes a third fin FET having L (L is an integer greater than M) fins¶0071-0076.
Regarding claim 7, Yu discloses wherein the first standard cell includes a first local interconnect extending in the second direction and connected to the first buried power line through a first via, the second standard cell includes a second local interconnect extending in the second direction and connected to the second buried power line through a second via, the third standard cell includes a third local interconnect extending in the second direction and connected to the third buried power line through a third via, the second via is larger in size than the first via, or the number of second vias is larger than the number of first vias, and the third via is larger in size than the second via, or the number of third vias is larger than the number of second vias Fig 3, 5, 7 and 10 ¶0071-0076.
Response to Arguments
Applicant’s arguments with respect to claims 1-7 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811