DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 5/25/2026 that has been entered, wherein claims 1-18 are pending and claims 1-6 are withdrawn.
Claim Rejections - 35 USC § 112
The rejection of claims 7-18 under 35 USC 112(b) are withdrawn in light of Applicant’s amendment of 5/25/2026.
Response to Arguments
Applicant’s arguments, see page 8, section II, filed 5/25/2026, with respect to the rejections of claims 7-18 under Liao (US 2022/0238358 A1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of newly found prior art references.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7-10, 12 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over An (US 2020/0294976 A1).
Regarding claim 7, An teaches a method for bonding an electronic component(Fig. 6), comprising:
providing a carrier substrate(100, ¶0033) having a carrying surface on which the electronic component(1, ¶0033) to be bonded is disposed and a non-carrying surface which is opposite to the carrying surface;
providing a target substrate(2, ¶0035) having a bonded surface and a non-bonded surface which is opposite to the bonded surface;
positioning the carrier substrate(100, ¶0033) and the target substrate(2, ¶0035) with the carrying surface of the carrier substrate(100, ¶0033) facing the bonded surface of the target substrate(2, ¶0035);
making the carrier substrate(100, ¶0033) and the target substrate(2, ¶0035) move toward each other until the electronic component(1, ¶0033) on the carrying surface of the carrier substrate(100, ¶0033) be in contact with the bonded surface of the target substrate(2, ¶0035);
applying a plurality of flexible pushes(positive pressure in 102, ¶0035) to the non-carrying surface of the carrier substrate(100, ¶0033) or to the non-bonded surface of the target substrate(2, ¶0035), in order for the electronic component(1, ¶0033) on the carrier substrate(100, ¶0033) to attain a more complete contact with the bonded surface of the target substrate(2, ¶0035).
The embodiment of Fig. 6 of An is not relied on to teach applying a thermal energy to bond the electronic component(1, ¶0033) onto the bonded surface of the target substrate(2, ¶0035) from the carrier substrate(100, ¶0033).
The embodiment of Fig. 8 of An, teaches applying a thermal energy(laser irradiation, ¶0041) to bond the electronic component(1, ¶0033) onto the bonded surface of the target substrate(2, ¶0035) from the carrier substrate(100, ¶0033). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of the embodiment of Fig. 6 of An, to include applying a thermal energy to bond the electronic component onto the bonded surface of the target substrate from the carrier substrate, as taught by the embodiment of Fig. 8 of An, in order to have rapid heating of all solders corresponding to the micro-LED chips in a short time(¶0041).
Regarding claim 8, An teaches the method for bonding the electronic component according to claim 7, wherein the plurality of flexible pushes(positive pressure in 102, ¶0035) are applied to the non-carrying surface of the carrier substrate(100, ¶0033) or to the non-bonded surface of the target substrate(2, ¶0035) respectively.
Regarding claim 9, An teaches the method for bonding the electronic component according to claim 8, wherein the plurality of flexible pushes(positive pressure in 102, ¶0035) are applied outward from a central portion of the non-carrying surface of the carrier substrate(100, ¶0033) or of the non-bonded surface of the target substrate(2, ¶0035).
Regarding claim 10, An teaches the method for bonding the electronic component according to claim 8, wherein the plurality of flexible pushes(positive pressure in 102, ¶0035) are applied from a side(backside) of the non-carrying surface of the carrier substrate(100, ¶0033) or of the non-bonded surface of the target substrate(2, ¶0035) to an opposite side thereto(front).
Regarding claim 12, An teaches the method for bonding the electronic component according to claim 7.
The embodiment of Fig. 6 of An is not relied on to teach the thermal energy is generated by a laser beam.
The embodiment of Fig. 8 of An, teaches the thermal energy(laser irradiation, ¶0041) to is generated by a laser beam(¶0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of the embodiment of Fig. 6 of An, so that the thermal energy is generated by a laser beam, as taught by the embodiment of Fig. 8 of An, in order to have rapid heating of all solders corresponding to the micro-LED chips in a short time(¶0041).
Regarding claim 16, An teaches the method for bonding the electronic component according to claim 7, further comprising applying a solder(3, ¶0041) to either the electronic component(1, ¶0033) or the bonded surface of the target substrate(2, ¶0035).
The embodiment of Fig. 6 of An is not relied on to teach applying a solder(3, ¶0041) to either the electronic component(1, ¶0033) or the bonded surface of the target substrate(2, ¶0035), prior to applying the thermal energy.
The embodiment of Fig. 8 of An, teaches applying a solder(3, ¶0041) to either the electronic component(1, ¶0033) or the bonded surface of the target substrate(2, ¶0035), prior to applying the thermal energy(laser irradiation, ¶0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of the embodiment of Fig. 6 of An, to include applying a solder to either the electronic component or the bonded surface of the target substrate, prior to applying the thermal energy the thermal energy is generated by a laser beam, as taught by the embodiment of Fig. 8 of An, in order to have rapid heating of all solders corresponding to the micro-LED chips in a short time(¶0041).
Regarding claim 17, An teaches the method for bonding the electronic component according to claim 7, wherein the electronic component(1, ¶0033) is a light-emitting diode (LED) chip(1, ¶0033).
Regarding claim 18, An teaches a method for manufacturing an LED display(1, 2,¶0035, ¶0001) comprising using the method of claim 17(please see claim 17) to bond the LED chip(1, ¶0033).
Claim 11 are rejected under 35 U.S.C. 103 as being unpatentable over An (US 2020/0294976 A1) as applied to claim 7 above further in view of Menguc et al. (US 11,107,948 B1) of record.
Regarding claim 11, An teaches the method for bonding the electronic component according to claim 7, but is not relied on to teach the plurality of flexible pushes(positive pressure in 102, ¶0035) are generated by a plurality of air bags.
Menguc teaches a method for bonding an electronic component(Figs. 2) wherein the plurality of flexible pushes(245, 250, col. 4, lines 36-44) are generated by a plurality of air bags(col. 4, lines 45-57). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Ah, so that the plurality of flexible pushes are generated by a plurality of air bags, as taught by Menguc, in order to facilitate alignment of the carrier substrate with the target substrate via an imaging device placed above the carrier substrate and so that each electronic component can be picked up and placed onto a target substrate independently(col. 3, line 65-col. 4, line 36).
Claim 13 are rejected under 35 U.S.C. 103 as being unpatentable over An (US 2020/0294976 A1) as applied to claim 7 above further in view of Chen (US 2021/0111148 A1).
Regarding claim 13, An teaches the method for bonding the electronic component according to claim 7, but is not relied on to teach the target substrate(2, ¶0035) is a thin film transistor (TFT) substrate.
Chen teaches a method for bonding an electronic component(Fig. 2) wherein the target substrate(5, ¶0067) is a thin film transistor (TFT) substrate(¶0067). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method as taught by An, so that the target substrate is a thin film transistor (TFT) substrate, as taught by Chen, in order to control the electronic component with a matrix circuit containing interlaced data lines and scan lines and a plurality of thin-film transistors(¶0067).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over An (US 2020/0294976 A1) as applied to claim 7 above further in view of Lee et al. (US 2007/0051295 A1) of record.
Regarding claim 14, An teaches the method for bonding the electronic component according to claim 7, but are not relied on to teach the plurality of flexible pushes(positive pressure in 102, ¶0035) are applied to the non-bonded surface of the target substrate(2, ¶0035).
Lee teaches a method for bonding an electronic component(Fig. 10) wherein the plurality of flexible pushes(air) are applied to the non-bonded surface of the target substrate(140, ¶0103). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of An, so that the plurality of flexible pushes are applied to the non-bonded surface of the target substrate, as taught by Lee, in order to bonding various-sized substrates including relatively large-sized substrates(¶0110).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over An (US 2020/0294976 A1) and Lee et al. (US 2007/0051295 A1) of record as applied to claim 14 above further in view of Brodoceanu et al. (US 2020/0111939 A1).
Regarding claim 15, An, in view of Lee, teaches the method for bonding the electronic component according to claim 14, but is not relied on to teach the thermal energy is applied to the carrier substrate(100, ¶0033).
Brodoceanu teaches a method for bonding an electronic component(Fig. 4) wherein he thermal energy(¶0037) is applied to the carrier substrate(120, ¶0037). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of An, so that he thermal energy is applied to the carrier substrate, as taught by Brodoceanu, in order selectively heat individual LEDs(¶0037).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
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