Prosecution Insights
Last updated: October 23, 2026
Application No. 18/447,333

ELECTRONIC PACKAGE STRUCTURE

Non-Final OA §102
Filed
Aug 10, 2023
Priority
Aug 12, 2022 — TW 111130489
Examiner
BOYLE, ABBIGALE A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Acer Incorporated
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
2m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
213 granted / 356 resolved
-8.2% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
13 currently pending
Career history
401
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.6%
+14.6% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 356 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings The drawings are objected to because the sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1. The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking. See Page(s) 1-4. The drawings contain improperly formatted lead lines because they are depicted as broken and/or hidden lines. Every lead line must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. Refer to 37 CFR 1.84(l) and 1.84(q). See Figure(s) 1. The drawings contain improper sectional views and/or sectional view references. The entire plane upon which a sectional view is taken should be indicated on the view from which the section is cut by a broken line. The ends of the broken line should be designated by Arabic or Roman numerals corresponding to the view number of the sectional view, and should have arrows to indicate the direction of sight. Hatching must be used to indicate section portions of an object, and must be made by regularly spaced oblique parallel lines spaced sufficiently apart to enable the lines to be distinguished without difficulty. Refer to 37 CFR 1.84(h(3)). See Figure(s) 1. The drawings contain reference characters having lead lines that are ambiguous. It is unclear which part of the drawing is referenced since it is unclear exactly what area the lead line is drawn to. Lead lines are those lines between the reference characters and the details referred to. They must originate in the immediate proximity of the reference character and extend to the feature indicated. Refer to 37 CFR 1.84(q). See Figure(s) 2-5. The drawings contain improper use of arrows. Arrows may be used at the ends of lines, provided that their meaning is clear, as follows: (1) On a lead line, a freestanding arrow to indicate the entire section towards which it points; (2) On a lead line, an arrow touching a line to indicate the surface shown by the line looking along the direction of the arrow; (3) To show the direction of movement; or (4) As part of a sectional view reference point line which is formatted as a broken line, the ends of which should have arrows to indicate the direction of sight. Refer to 37 CFR 1.84(r). See Figure(s) 1-5. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Multi-device Package Having Passive Devices Sealed from Thermal Interface Material of Semiconductor Device. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsuchida et al. (U.S. 2022/0262759). Regarding Claim 1, Tsuchida et al., Figures 5-9, discloses an electronic package structure, comprising: a substrate (substrate 17); a first electronic component disposed on the substrate (first electronic component 11); at least one second electronic component disposed on the substrate and adjacent to the first electronic component (second electronic components 16); an insulating film disposed on the at least one second electronic component and the substrate (insulating films 115 or 115M or 215 or 225 or 225/215); an insulating glue disposed on the at least one second electronic component and the substrate and covering at least part of the insulating film (insulating glue E1 or 115 or E2 or 33); a liquid metal disposed on the first electronic component (liquid metal 31, [0038]; and a heat-dissipating plate disposed on the first electronic component and squeezing the liquid metal, wherein the insulating film and the insulating glue prevent the overflowing liquid metal from contacting the at least one second electronic component and the substrate (heat-dissipating plate 50, [0093]). Regarding Claim 2, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 1, further comprising a retaining wall disposed on the substrate and surrounding the first electronic component, the at least one second electronic component, the insulating film, the insulating glue, and the liquid metal (retaining wall 33 and/or 14 and/or E1). Regarding Claim 3, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 2, wherein an outer edge of the insulating film is sandwiched between the heat-dissipating plate and the retaining wall (insulating films 115 or 215 or 225 or 225/215, retaining wall 14, heat-dissipating plate 50). Regarding Claim 4, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 3, further comprising another insulating glue disposed between the retaining wall and the heat-dissipating plate, wherein the outer edge of the insulating film is sandwiched between the another insulating glue and the retaining wall (another insulating glue E1 or 33 or 215 or 215/33, insulating film 115 or 225/215 or 225, heat-dissipating plate 50, retaining wall 14). Regarding Claim 5, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 3, further comprising another insulating glue disposed between the retaining wall and the heat-dissipating plate, wherein the outer edge of the insulating film is sandwiched between the another insulating glue and the heat-dissipating plate (another insulating glue 225, insulating film 215, heat-dissipating plate 50, retaining wall 14). Regarding Claim 6, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 1, wherein an inner edge of the insulating film surrounds the first electronic component and is partially covered by the insulating glue (first electronic component 11, insulating films 115 or 115M or 215 or 225 or 225/215, insulating glue E1 or 115 or E2 or 33). Regarding Claim 7, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 6, wherein the inner edge of the insulating film is pressed on the at least one second electronic component by the insulating glue (insulating films 115 or 115M or 215 or 225 or 225/215, insulating glue E1 or 115 or E2 or 33). Regarding Claim 8, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 6, wherein the inner edge of the insulating film is disposed between the first electronic component and the at least one second electronic component (insulating films 115 or 115M or 215 or 225 or 225/215, first electronic component 11, second electronic component 16). Regarding Claim 9, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 1, wherein an inner edge of the insulating film and part of the insulating glue overlap on the at least one second electronic component (insulating films 115 or 115M or 215 or 225 or 225/215, insulating glue E1 or 115M or E2 or 33, second electronic component 16). Regarding Claim 10, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 1, further comprising a fixing glue disposed on the substrate and at a periphery of the first electronic component to fix the first electronic component on the substrate, wherein a gap exists between the at least one second electronic component and the fixing glue, and part of the insulating glue fills the gap (fixing glue 23, substrate 17, first electronic component 11, second electronic component 16, fixing glue 23, insulating glue E1 or 115 or E2 or 33). Regarding Claim 11, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 10, wherein the insulating glue covers part of the fixing glue (insulating glue E1 or E2, fixing glue 23, [0069]). Regarding Claim 12, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 1, comprising a plurality of second electronic components disposed on the substrate and at a periphery of the first electronic component, wherein the second electronic components are disposed in different radial directions relative to the first electronic component, and the insulating film covers part of the second electronic components with a smallest radial dimension and rest of the second electronic components (second electronic components 16, substrate 17, first electronic component 11, insulating films 115 or 115M or 215 or 225 or 225/215,). Regarding Claim 13, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 2, wherein the heat-dissipating plate, the substrate, and the retaining wall form a space, and the first electronic component, the at least one second electronic component, the insulating film, the insulating glue, and the liquid metal are within the space (Space S, see Figure 1b). Regarding Claim 14, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 13, wherein the insulating glue is in contact with the heat-dissipating plate and divides the space into a first subspace and a second subspace, the liquid metal is in the first subspace, and a part where the insulating film is not covered by the insulating glue is in the second subspace (insulating glue E1 or E2 or 33, heat-dissipating plate 50, liquid metal 31, insulating films 115 or 215 or 225 or 225/215). Regarding Claim 15, Tsuchida et al., Figures 5-9, further discloses the electronic package structure according to claim 1, wherein the first electronic component is a die, and the at least one second electronic component is a capacitor (first electronic component 11, second electronic component 16, [0031]). Conclusion Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Abbigale Boyle whose telephone number is 571-270-7919. The Examiner can normally be reached from 11 A.M to 7 P.M., Monday through Friday. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Zandra Smith, can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance form a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Abbigale Boyle Examiner, Art Unit 2899 /ABBIGALE A BOYLE/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Aug 10, 2023
Application Filed
Oct 05, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
72%
With Interview (+12.6%)
3y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 356 resolved cases by this examiner. Grant probability derived from career allowance rate.

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