DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
1. Claims 13-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/1/25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 8 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
3. Claim 8 recites the limitation " the second insulating layer ". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2021/0243369 Choi et al.
4. Referring to claim 1, Choi et al. teaches a method of manufacturing a light emitting element, the method comprising: forming a first semiconductor layer, (Figure 5A-J #122), on a substrate, (Figure 5A-J #101); patterning a first insulating layer, (Figure 5A-J #141), on a side surface of the first semiconductor layer, (Figure 5A-J #122); and forming an active layer, (Figure 5A-J #125), and a second semiconductor layer, (Figure 5A-J #127), on the first semiconductor layer, (Figure 5A-J #122).
5. Referring to claim 2, Choi et al. teaches a method of claim 1, wherein the patterning of the first semiconductor layer comprises: forming a base semiconductor layer, (Figure 5A-J #122’), on the substrate, (Figure 5A-J #101); and etching, (Paragraph 0026), at least a portion of the base semiconductor layer, (Figure 5A-J #122’), by using a mask, (Figure 5A-J #122), exposing an upper surface, (Figure 5A-J upper surface area between #122N), of the base semiconductor layer, (Figure 5A-J #122’).
6. Referring to claim 3, Choi et al. teaches a method of claim 2, wherein the patterning of the first semiconductor layer, (Figure 5A-J #122), and the forming of the second semiconductor layer, (Figure 5A-J #127), are performed in separate processes, (Paragraph 0021).
7. Referring to claim 4, Choi et al. teaches a method of claim 2, wherein the forming of the active layer, (Figure 5A-J #125), and the second semiconductor layer, (Figure 5A-J #127), comprises depositing the active layer, (Figure 5A-J #125), and the second semiconductor layer, (Figure 5A-J #127), and the depositing of the active layer, (Figure 5A-J #125), and the second semiconductor layer, (Figure 5A-J #127), comprises individually patterning the active layer and the second semiconductor layer, (Paragraph 0021).
8. Referring to claim 5, Choi et al. teaches a method of claim 1, wherein the patterning of the first insulating layer, (Figure 5A-J #141), comprises exposing an upper surface of the first semiconductor layer, (Figure 5A-J where the upper surface of #122 in the area of #132 is exposed from the insulating layer #141 in Figure 5G), from the first insulating layer, (Figure 5A-J #141).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 8, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2013/0099199 Cha et al.
9. Referring to claim 1, Cha et al. teaches a method of manufacturing a light emitting element, the method comprising: forming a first semiconductor layer, (Figure 5A-I #520), on a substrate, (Figure 5A-I #512); patterning a first insulating layer, (Figure 5A-I #527), on a side surface of the first semiconductor layer, (Figure 5A-I #520); and forming an active layer, (Figure 5A-I #523), and a second semiconductor layer, (Figure 5A-I #525), on the first semiconductor layer, (Figure 5A-I #520).
10. Referring to claim 4, Cha et al. teaches a method of claim 2, wherein the forming of the active layer, (Figure 5A-I #523), and the second semiconductor layer, (Figure 5A-I #525), comprises depositing the active layer, (Figure 5A-I #523), and the second semiconductor layer, (Figure 5A-I #525), and the depositing of the active layer, (Figure 5A-I #523), and the second semiconductor layer, (Figure 5A-I #525), comprises individually patterning the active layer and the second semiconductor layer, (Paragraph 0054).
11. Referring to claim 8, Cha et al. teaches a method of claim 1, further comprising: patterning the second insulating layer, (Figure 5A-I #535 & Paragraph 0055), wherein the patterning of the second insulating layer comprises: disposing a first portion of the second insulating layer, (Figure 5A-I lateral portion of #535), on the first insulating layer, (Figure 5A-I #527); and disposing a second portion of the second insulating layer, (Figure 5A-I vertical portion of #535), on a side surface of the active layer, (Figure 5A-I #523), and a side surface of the second semiconductor layer, (Figure 5A-I #525).
12. Referring to claim 11, Cha et al. teaches a method of claim 1, further comprising: forming an additional first-semiconductor-layer on the first semiconductor layer, (Figure 5A-I #520 & Paragraph 0054 where layer #520 is grown, hence forming additional layers on top of each other).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
13. Claims 6, 7, 9, 10, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
14. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the method of claim 5, wherein the forming of the active layer and the second semiconductor layer comprises growing the active layer and the second semiconductor layer on the exposed upper surface of the first semiconductor layer; the method of claim 8, further comprising: patterning an electrode layer on the second semiconductor layer after the patterning of the second insulating layer; the method of claim 1, wherein the first semiconductor layer, the active layer, and the second semiconductor layer form a semiconductor stack member, the first semiconductor layer comprises first semiconductor layers adjacent to each other, the method further comprising: forming a lower active layer and a lower second-semiconductor-layer between the first semiconductor layers adjacent to each other at a same time to forming the active layer and the second semiconductor layer; and separating the semiconductor stack member from the substrate, the separating of the semiconductor stack member comprises individually separating the semiconductor stack member along a separation line that is a portion of the first semiconductor layer, and the separation line is defined at a position substantially identical to or higher than an uppermost surface of the lower second-semiconductor-layer; and/or he method of claim 11, further comprising: forming the active layer and the second semiconductor layer on the additional first-semiconductor-layer, and wherein a surface area of an upper surface of the first semiconductor layer, on which the additional first-semiconductor-layer grows, is smaller than a surface area of a proximity surface between the additional first-semiconductor-layer and the active layer.
Conclusion
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 2/5/26