DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeoka et al. US 2013/0037779.
Regarding claim 1, Takeoka discloses an epitaxial structure of a light-emitting device, comprising a first semiconductor layer (9, fig. 1 and paragraph 0058), an active region (12, 14, fig. 1 and paragraph 0058) and a second semiconductor layer (16, fig. 1 and paragraph 0058) sequentially stacked;
wherein the active region comprises at least two groups of a barrier layer (14A, fig. 3 and paragraphs 0058 and 0091) and a quantum well layer (14W, fig. 3 and paragraphs 0058 and 0091) which are stacked, a surface of the quantum well layer away from the first semiconductor layer has a first roughness, a surface of the barrier layer away from the first semiconductor layer has a second roughness, and the first roughness is greater than the second roughness (15, fig. 1 discloses V pits, and fig. 6C discloses wherein V pits are formed with a starting point on average in layer 12 (P section, paragraph 0075, 0109) and with a starting point on average in layer 14 (N section, paragraphs 0145-0154) note: this is the average starting point of the V pits, which means some V pits are formed higher than the average by definition, as such the summation of the V pits as progressed from layer 12 through layer 14 would give rise to a surface roughness that increases for each additional layer, therefore the surface of a quantum well layer at position 14W1, fig. 3 would have a rougher surface than a surface of the barrier layer at position 14A6 since layer 14W1 would contain more and wider V pits than layer 14A6)
Regarding claim 2, Takeoka further discloses wherein the surface of the quantum well layer away from the first semiconductor layer is provided with at least one first recess (14W1, fig. 3), and the surface of the barrier layer (14A6, fig. 3) away from the first semiconductor layer is provided with at least one second recess (V pits of 15, figs. 1 and 6C);
wherein an average depth of the first recess per unit area is greater than an average depth of the second recess per unit area, and a direction of the depth is perpendicular to a plane where the first semiconductor layer is located, such that the first roughness is greater than the second roughness (fig. 6C).
Regarding claim 3, Takeoka further discloses wherein for each of the at least one first recess, the depth of the first recess is 0.5nm to 5nm; or, the first recess has a width of 0.5nm to 5nm in a direction parallel to the plane where the first semiconductor layer is located (fig. 6C and paragraph 0095, note: recess in 14 is either partial or entirely through 14).
Regarding claim 4, Takeoka further discloses wherein the surface of the quantum well layer away from the first semiconductor layer is provided with at least one first recess, the at least one first recess comprises a V-pit, and the quantum well layer where the V-pit is located is formed with a semi-polar or non-polar face (14, figs. 1, 6C and paragraph 0075).
Regarding claim 5, Takeoka further discloses wherein the surface of the barrier layer away from the first semiconductor layer is flat (112, fig. 8 and paragraphs 0168-0172).
Regarding claim 6, Takeoka further discloses wherein a material of the barrier layer comprises a III-V compound semiconductor material (paragraph 0084), and a material of the quantum well layer comprises a III-V compound semiconductor material (paragraph 0093).
Regarding claim 7, Takeoka further discloses wherein the material of the quantum well layer is InGaN or InAlGaN, wherein a ratio of the-an In component is greater than 5% (paragraph 0093).
Regarding claim 8, Takeoka further discloses wherein a thickness of the barrier layer in a direction perpendicular to a plane where the first semiconductor layer is located is 3nm to 20nm, and/or, a thickness of the quantum well layer in a direction perpendicular to a plane where the first semiconductor layer is located is 0.5nm to 20nm (paragraph 0095).
Regarding claim 9, Takeoka further discloses wherein the thickness of the barrier layer (paragraph 0088) is greater than the thickness of the quantum well layer (paragraph 0095).
Regarding claim 10, Takeoka further discloses further comprising a third semiconductor layer (209, fig. 10) between the first semiconductor layer (8, fig. 10) and the active region (14, fig. 10), wherein the third semiconductor layer comprises at least one group of a first sub- layer and a second sub-layer which are stacked, a surface of the first sub-layer away from the first semiconductor layer has a third roughness (210,fig. 10), a surface of the second sub-layer away from the first semiconductor layer has a fourth roughness (dashed line between 209 and 8, fig. 10), and the third roughness is greater than the fourth roughness (fig. 10 and paragraphs 0179-0193).
Regarding claim 11, Takeoka further discloses wherein the first sub-layer has the same material as the quantum well layer in the active region, and the second sub-layer has the same material as the barrier layer in the active region (paragraphs 0182-0193).
Response to Arguments
Applicant's arguments filed 3/6/26 have been fully considered but they are not persuasive. Applicant has amended the independent claim to include the limitation that the active region comprises at least two groups of a barrier layer and a quantum well layer which are stacked and argues that Takeoka does not teach such layers with the claimed roughness features. Examiner disagrees, as mentioned in the above rejection, Takeoka explicitly discloses at least two groups of a barrier layer and a quantum well layer (14A, 14W, fig. 3 and paragraph 0091) for which a surface roughness of these layers would increase from layer 12 towards layer 16 as a result of the cumulative insertion of the V pits as mentioned in the above rejection. However, Examiner notes that there are differences in Applicant’s invention. For instance, Applicant’s figures 7 and 8 appear to show that all top surfaces of quantum well layers 202 have the same roughness and all top surfaces the barrier layers 201 appear to have the same roughness, for which the top surface of the quantum well layers have a greater roughness. Applicant is advised to amend the claim language to distinguish from the prior art of record.
Applicant further argues that the limitations of claim 3 are not met. Examiner disagrees. As mentioned in the above rejection, the ranges of claim 3 would be met since Takeoka discloses that V pits are formed in layer 14 as mentioned in the above rejection. Furthermore, claim 5 arguments are not persuasive because Takeoka discloses a flat surface between the V pits.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 3/16/26