DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/16/2025 is acknowledge.
It is argued that the applicant submits that removal of the dummy nitride layers is necessary for the word line layer to achieve "a gate region that has a sidewall that has a reverse dome shape" as recited in claim 1 of Group I. However, the restriction is made on the device as claimed.
Furthermore, the applicant argues that the Examiner will likely find the same list of references in a search for prior art relating to Group I and Group II, and thus there is no undue burden to examine claims 15-20 of Group II with the claims of Group I.
However, MPEP 808.02 identifies 3 options to support the burden requirement:
1) different field of search
2) separate classification with separate field of search
3) separate status with separate field of search
Each of these requirements includes a separate field of search component. Separate field of search means it is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 lines 5 and line 22 recites “a first direction”. It is unclear if the two recitations are referring a same first direction. As such the claim is unclear and indefinite.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 7, 8-9, 11 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHEN 20220254803.
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Regarding claim 1, fig. 1 of Shen discloses a three-dimensional memory device, comprising:
a plurality of alternating layers formed over a surface of a substrate (201/202), wherein the plurality of alternating layers comprise word line layers 911-918 (par [0025]) and inter-word line dielectric layers 210s that are sequentially stacked in a first direction Z, wherein each of the word line layers has a gate region that has a sidewall that has a reverse dome shape (par [0027] word line material has recessed inside surfaces – as per applicant specification - a reverse dome shape (e.g., recesses 512 in FIG. 5B) – par [0048] of applicant);
a channel 401 having a first end coupled to a source line 701, a second end coupled to a drain line 702 (see figs. 1A-1B showing coupling configuration), and extending in the first direction between the source line and the drain line; and
an ONO layer stack 928 (par [0030]) disposed between the gate regions (left and right regions of fig. 1B) and the channel 401, wherein the ONO layer stack extends in the first direction between the source line and the drain line (see figs. 1A-1B).
Regarding claim 8 (see claim 1 rejection above), figs. 1A-B of Shen discloses a three-dimensional memory device, comprising:
a plurality of alternating layers formed over a surface of a substrate, wherein the plurality of alternating layers comprise word line layers and inter-word line dielectric layers that are sequentially stacked in a first direction, wherein each of the word line layers has a gate region that has a sidewall that has a reverse dome shape;
a channel having a first end coupled to a source line, a second end coupled to a drain line, and extending in the first direction between the source line and the drain line; and
an ONO layer stack disposed between the gate regions and the channel, wherein the ONO layer stack comprises a first oxide layer, a first silicon nitride layer and a second oxide layer and extends in the first direction between the source line and the drain line, and
wherein: the first oxide layer conforms to the reverse dome shape of the sidewall; the first silicon nitride layer is disposed between the first oxide layer and the second oxide layer (this necessary the case as shown in fig. 1B);
the first silicon nitride layer has a first portion that substantially fills a space formed in the gate regions between the reverse dome shape of the first oxide layer and a surface of the second oxide layer (this is necessary the case as ONO, the N is between the left O and the right O);
the first silicon nitride layer has a plurality of second portions (left horizontal portion and right horizontal portion in figs. 1A-1B) that are disposed over each of the inter-word line dielectric layers portions (see fig. 1A showing ONO is over horizontal surface of 210) and between gate regions (portion over recessed inside surfaces which are between left gate region and right gate region as shown in figs. 1A-B); and
a thickness of the first silicon nitride layer in a first direction is less over a surface of the inter-word line dielectric layers (vertical thickness at sharp point at top or bottom tip on top of recess) than a thickness of the first silicon nitride layer in the first direction over the gate regions of the word line layers (thickness between top and bottom tips of recess).
Regarding claims 2 and 9, fig. 1A of Shen necessary discloses wherein the ONO layer stack comprises a first silicon nitride layer formed within the three-dimensional memory device, and wherein the first silicon nitride layer comprises a half cylinder shape in each of the gate regions of the word line layers within the plurality of alternating layers.
Regarding claims 4 and 11, fig. 1A of Shen necessary discloses wherein the ONO layer stack further comprises: a first oxide layer disposed on the word line layers and inter-word line dielectric layers; a second oxide layer disposed on the first silicon nitride layer; a channel layer 401 disposed on the second oxide layer; and a filler layer 510 disposed on the channel layer.
Regarding claims 7 and 14, fig. 1A of Shen discloses wherein the offsetting layer is configured to offset a position of the word line layers.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shen.
Regarding claims 3 and 10, Shen discloses claim 2 and 9. Shen does not disclose wherein the reverse dome shape is formed on the sidewall using a recessing process that comprises: preferentially etching a dummy nitride layer formed between the inter-word line dielectric layers before the word line layer, wherein the preferential etching of the dummy nitride layer causes a reverse dome shape to be formed in the dummy nitride layer; depositing the ONO stack; and forming the word line layer over the ONO stack.
However, Applicant’s claims 3 and 10 do not distinguish over the Shen reference regardless of the process used to form the encapsulated air gap because only the final product is relevant, not the process of making such as “wherein the reverse dome shape is formed on the sidewall using a recessing process that comprises: preferentially etching a dummy nitride layer formed between the inter-word line dielectric layers before the word line layer, wherein the preferential etching of the dummy nitride layer causes a reverse dome shape to be formed in the dummy nitride layer; depositing the ONO stack; and forming the word line layer over the ONO stack”.
Note that a “product by process claim " is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1].
Claims 5-6 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Shen in view of Pang et al. 20170345705.
Regarding claims 5-6 and 12-13, Shen does not disclose further comprising an offsetting layer disposed between the word line layer and the inter-word line dielectric layer and wherein the offsetting layer is a silicon oxide layer that is doped.
However, Pang discloses a three-dimensional memory device and discloses techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.
In view of such teaching, it would have been obvious to form a device of Shen further comprising an offsetting layer disposed between the word line layer and the inter-word line dielectric layer and wherein the offsetting layer is a silicon oxide layer that is doped such as taught by Pang to reduced neighboring word line interference by reducing dielectric constant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893