Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 2-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Publication No. 2019/0122969) in view of Kroeninger et al. (US Publication No. 2009/0261468).
Regarding claim 2, Lee discloses an application manufacturing method of a fan-out chip-embedded packaging process, the application manufacturing method comprising the steps of:
preforming integrated circuit dies (71b/71c) into a plurality of implementation units, the implementation units comprising a plurality of chips (71b/71c) of different thicknesses, and the chips being equipped with electrically conductive pillars of different heights respectively (the pillars on top of each chip are of different heights), each of the chips and the respective electrically conductive pillars being covered by an insulating gel (the gel covers the pillars) to become a preformed unit (71b/71c) (paragraph 28)
then using a carrier to form a plurality of carrying regions (70b/70c) for the aforementioned preformed units to be glued therein (Figures 7A-7B)
forming an insulating layer (72) by gel injection molding to make it completely seal the preformed units (Figure 7C)
performing a grinding process (paragraph 48 – laser drilling)
arranging wires (74) to connect each of the electrically conductive pillars (below 74) of the chips with the adjacent chip, thereby forming a complete wire arrangement (paragraphs 47-50)
forming an insulating layer by gel injection molding (75) again to cover the wires (74) and making exposing guiding holes, thereby accomplishing a frontside packaging process (holes are created for solder balls 76)
removing the carrier to accomplish a singulation process (paragraph 56 – sawing at least partially removes some of the carrier)
Lee does not disclose completely removing a temporary carrier. However, Kroeninger discloses a temporary carrier (1) on which preformed dies (3) are formed (Figure 3D), followed by removal of the carrier (Figure 3F). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have combined the feature of using a temporary carrier of Koeninger with the packaging of Lee, since it can allow for electrical connections on both sides of the device, improving versatility and density of the device, while spreading out thermal dissipation to both sides of the device (paragraphs 23-24).
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Regarding claim 3, Lee discloses on the carrier of the step b), high electrically conductive pillars being used to form a plurality of carrying rooms for the preformed units of the step a) to be glued therein, continuing the steps c), d) and e) to accomplish arranging electrically conductive wires (70) underneath to add another backside packaging process (die pads 70 are conductive wiring on the back side of the package).
Regarding claim 4, Lee discloses an application manufacturing method of a fan-out chip-embedded packaging process, the application manufacturing method comprising the steps of:
preforming integrated circuit dies (71b/71c) into a plurality of implementation units, the implementation units comprising a plurality of chips (71b/71c) of different thicknesses (the pillars on top of each chip are of different heights) (Figure 7A), and the chips being equipped with electrically conductive pillars of different heights respectively (paragraph 28), each of the chips and the respective electrically conductive pillars being covered by an insulating gel to become a preformed unit (the gel covers the pillars)
gluing (adhesive below chips 71b/71c) the preformed units of the step a) separately on a carrier (70) to form a unit module (Figure 7A-7B)
molding an insulating gel (covering the pillars) on the unit module of the step b) to form a package forming unit (71b/71c)
then continuing to arrange the package forming unit (71b/71c) of the step c) with connecting wires (73) to connect the adjacent preformed units according to requirements (Figure 7D)
molding an insulating gel (75) again on the connecting wires of the step d), and forming openings (openings in 75) at appropriate positions for subsequent crystal growth (76)
removing the carrier of the step b) to accomplish unit fan-out chip packaging by singulation (paragraph 56)
Lee does not disclose completely removing a temporary carrier. However, Kroeninger discloses a temporary carrier (1) on which preformed dies (3) are formed (Figure 3D), followed by removal of the carrier (Figure 3F). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have combined the feature of using a temporary carrier of Kroeninger with the packaging of Lee, since it can allow for electrical connections on both sides of the device, improving versatility and density of the device, while spreading out thermal dissipation to both sides of the device (paragraphs 23-24).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Publication No. 2019/0122969) in view of Kroeninger et al. (US Publication No. 2009/0261468), further in of Mao et al. (US Publication No. 2024/0136238), and further in view of Ji et al. (US Publication No. 2020/0219846).
Regarding claim 5, Lee/Kroeninger discloses the limitations as discussed in the rejection of claim 4 above. Lee also discloses the steps of:
preforming integrated circuit dies (71b/71c) into an implementation unit, the implementation unit comprising a plurality of chips (71b/71c) of different thicknesses (the pillars on top of each chip are of different heights), and the aforementioned chips being equipped with electrically conductive pillars of different heights respectively (Figure 7A)
vertically setting a plurality of high electrically conductive pillars on a carrier (70) to form a plurality of carrying regions, the high electrically conductive pillars (74) being higher in height than the above-mentioned electrically conductive pillars of the chips (Figure 7D)
covering the chip with a packaging gel (the gel covers the pillars); gluing and preforming the plurality of chips of different thicknesses (Figure 7B) of the step a) in the carrying regions (70) of the step b) respectively
forming an insulating layer by gel injection molding (72/75) in a way that space surrounding the high electrically conductive pillars and the chips of the steps b) and c) is filled with injected insulating gel to be completely sealed so that the high electrically conductive pillars and the chips of the step c) are completely covered in the insulating layer (72/75) (Figure 7E)
performing a grinding process by grinding downwardly toward outer edges of the electrically conductive pillars of the chips and the high electrically conductive pillars of the step d) until the high electrically conductive pillars and the electrically conductive pillars of the chips are exposed by grinding (paragraph 48 – laser drilling)
arranging wires (74) to connect each of the electrically conductive pillars of the chips (71b/71c) with the adjacent high electrically conductive pillar, thereby forming a complete wire arrangement (Figure 7D)
forming an insulating layer by gel injection molding (75) again thereon to firstly cover the wires (74), and then performing an etching process at specific positions to make exposing guiding holes (76) (Figure 7E)
k) dicing a chip module accomplished by the above-mentioned step a) to step j) from a wafer, thereby forming a predetermined number of fan-out packaging preformed units (paragraph 56)
Lee/ Kroeninger does not clearly disclose removing the carrier to further perform a chip back grinding process until a back of the earliest exposed chip is exposed to outside. However, Mao discloses removing the carrier (102) by back grinding to the earliest chip (306) to be exposed to the outside (Figures 6-7. It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Lee to back grind down the back to the earliest chip, as taught by Mao, since it allows for attachment of a heat sink for improved heat spreading to improve device performance and longevity (paragraph 18).
Lee/Kroeninger also does not clearly disclose arranging wires again on the backs of the chips, thereby forming a predetermined connecting wire arrangement, and performing a back insulating layer molding process again to form a protecting layer; then performing an etching process to further form exposing guiding holes. However, Ji discloses an embodiment which includes a back mold (1) protecting a chip (71) and exposing guiding holes for external interconnection (4-a) (Figure 20A). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the package of Lee to include the back protection and guiding holes, as taught by Ji, since it can improve symmetry of the circuit, reducing parasitic inductance, density, and heat dissipation (paragraph 42).
Regarding claim 6, Ji discloses a step of continuing to make a heat dissipation layer (4-a) on an exposed portion of the back of the chip between the step j) and the step k) (Figure 20A). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the disclosure of Lee in view of Mao, and further in view of Ji.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.R.P/ 2/8/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897