DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on Feb. 10th 2026 is acknowledged. Claims 1-15 and 21-25 remain pending in the application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claim 11 is objected to because of the following informalities:
In claim 11, line 13, “a fourth semiconductive nanostructure" should read “the fourth semiconductive nanostructure”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the second pull-down transistor overlaps with the second pull-down transistor" in lin. 1-2. There is insufficient antecedent basis for this limitation in the claim. This limitation just requires the second pull-down transistor overlaps itself, which make people confused. For examination purposes, examiner has interpreted "the second pull-down transistor overlaps with the second pull-down transistor" to be consistent with the cited prior art.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9-10 and 21 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Liaw et al. (US 20160078922), hereinafter Liaw.
Regarding claim 1, Liaw teaches a method (Abstract), comprising:
forming a first pull-up transistor (Annotated fig. 12, left square, pull-up transistor PU-1 at H1; para. 0019) and a first pass-gate transistor (pass-gate transistor PG-1 at H1; para. 0019) over a substrate (substrate 20; para. 0022) at a first level height (H1, as device put vertical as the paper), the first pull-up (PU-1) and first pass-gate transistors (PG-1) being of a dual port static random access memory (SRAM) cell (two SRAM cell 10 in the square; para. 0019);
forming a first pull-down transistor (pull-down transistor PD-2 at H2; para. 0019) and a second pass-gate transistor (pass-gate transistor PG-2 at H2; para. 0019) of the dual port SRAM cell (10) over the substrate (20) at a second level height (H2);
forming a second pull-down transistor (PD-2 at H3) and a third pass-gate transistor (PG-2 at H3) of the dual port SRAM cell (10) over the substrate (20) at a third level height (H3); and
forming a second pull-up transistor (PU-1 at H4) and a fourth pass-gate transistor (PG-1 at H4) of the dual port SRAM cell (10) over the substrate (20) at a fourth level height (H4).
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(Annotated fig. 12)
Regarding claim 2, Liaw teaches the method of claim 1, wherein the second pass-gate transistor (Annotated fig. 12, PG-2 at H2) overlaps (along diagonal direction) with the first pass-gate transistor (PG-1 at H1), and the second pull-down transistor (PD-2 at H2) overlaps (along diagonal direction) with the second pass-gate transistor (PG-2 at H2).
Regarding claim 3, Liaw teaches the method of claim 2, wherein the second pull-down transistor (Annotated fig. 12, PD-2 at H2) overlaps with the second pull-down transistor (PD-2 at H2 itself or PD-1 at H1).
Regarding claim 9, Liaw teaches the method of claim 1, wherein the first and second pull-up transistors (Annotated fig. 12, PD-2 at H2, H3), the first and second pull-down transistors (PU-1 at H1, H4), and the first, second, third, and fourth pass-gate transistors (PG-1 at H1, H4 and PG-2 at H2, H3) are formed in a sequential manner (sequential manner as the patterns in the left square to the right of fig. 12) over the substrate (20) at the respective first, second, third, and fourth level heights (H1-H4).
Regarding claim 10, Liaw teaches the method of claim 1, wherein at least one of the first and second pull-up transistors (Annotated fig. 12, PU-1 at H1, H4), the first and second pull-down transistors (PD-2 at H2, H3), and the first, second, third, and fourth pass- gate transistors (PG-1 at H1, H4 and PG-2 at H2, H3) of different level heights (H1-H4) is formed separately (H3 and H2 are separately) and then combined through bonding (by strap cells 114; para. 0047) to form the dual port SRAM cell (two SRAM cell 10).
Regarding claim 21, Liaw teaches a method (Abstract), comprising:
forming first and second transistors (Annotated fig. 12, pull-down transistor PD-1, pass-gate transistor PG-1 at H1; para. 0019) over a substrate (substrate 20; para. 0022), the first and second transistors (PD-1, PG-1) being of a static random access memory (SRAM) cell (four SRAM cell 10; para. 0019), and the first and second transistors being of a first conductivity type (PD-1, PG-1 are N-type; para. 0019);
forming third and fourth transistors (left and right pull-up transistor PU-2 at H2) of the SRAM cell (10) over the first and second transistors (PD-1, PG-1 at H1), the third and fourth transistors (PU-2 at H2) being of a second conductivity type (PU2 are P-type) opposite to the first conductivity type (N-type);
forming fifth and sixth transistors (left and right PU-2 at H3) of the SRAM cell (10) over the third and fourth transistors (PU-2 at H2), the fifth and sixth transistors (PU-2 at H3) being of the second conductivity type (P-type); and
forming seventh and eighth transistors (PD-1, PG-1 at H4) of the SRAM cell (10) over the fifth and sixth transistors (PU-2 at H3), the seventh and eighth transistors being of the first conductivity type (PD-1, PG-1 are N-type).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-7, 11-15 and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Paul et al. (US 20200035686).
Regarding claim 4, Liaw teaches the method of claim 1, further comprising: a fifth level height (Annotated fig. 12, H5) higher than the second level height (H2), and lower than the third level height (H3).
Liaw fails to explicitly teach forming a cross coupling line of the dual port SRAM cell, the cross coupling line laterally extending at a fifth level height.
However, Paul teaches forming a cross coupling line (Paul: fig. 2, cross-connect line 205A, 205B; para. 0022) of the dual port SRAM cell (Paul: two port SRAM cell; para. 0001), the cross coupling line (Paul: 205A, 205B) laterally extending (horizontal direction) at a fifth level height (middle level as H5 of Liaw).
Paul and Liaw are considered to be analogous to the claimed invention because they are in the same field of SRAM devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the cross coupling line as taught by Paul.
Doing so would realize an interconnect structure to reduce the cell area that allows smaller devices to be fabricated (Paul: para. 0003).
Regarding claim 5, Liaw teaches the method of claim 1, further comprising: a fifth level height (Annotated fig. 12, H5) higher than the second level height (H2), and lower than the third level height (H3).
Liaw fails to explicitly teach forming a voltage source line of the dual port SRAM cell, the voltage source line laterally extending at a fifth level height.
However, Paul teaches forming a voltage source line (Paul: fig. 2, VDD contact 230A, 230B; para. 0024) of the dual port SRAM cell (Paul: two port SRAM cell; para. 0001), the voltage source line laterally extending (laterally into the paper) at a fifth level height (middle level as H5 of Liaw).
Paul and Liaw are considered to be analogous to the claimed invention because they are in the same field of SRAM devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the voltage source line as taught by Paul.
Doing so would realize an interconnect structure to reduce the cell area that allows smaller devices to be fabricated (Paul: para. 0003).
Regarding claim 6, Liaw in view of Paul teaches the method of claim 5, further comprising:
forming a first ground line (Paul: fig. 2, VSS contact 225B; para. 0024) of the dual port SRAM cell (Paul: two port SRAM cell), the first ground line (Paul: 225B) laterally extending (laterally into the paper) between the voltage source line (Paul: 230B) and the first pull-down and the second pass-gate transistors (Paul: pull-up transistor PU1 and pass gate transistor PG1; para. 0019, similar to PU-1, PG-1 at H1 of Liaw).
Regarding claim 7, Liaw in view of Paul teaches the method of claim 6, further comprising:
forming a second ground line (Paul: fig. 2, VSS contact 225A; para. 0024) of the dual port SRAM cell (Paul: two port SRAM cell), the second ground line (Paul: 225A) laterally extending (laterally into the paper) between the voltage source line (Paul: 230A) and the second pull-down and third pass-gate transistors (Paul: pull-down transistor PU2 and pass gate transistor PG2; para. 0019, similar to PD-2, PG-2 at H3 of Liaw).
Regarding claim 11, Liaw teaches a method (Abstract), comprising:
forming a first semiconductive nanostructure (Annotated fig. 12, left square, channel at H1, channel are nano-bars; para. 0038), and a second semiconductive nanostructure (channel at H2) vertically arranged with respect to the first semiconductive nanostructure (channel at H1);
forming a plurality of first epitaxial structures (fig. 4 as the detail structure at H1 or H2, drain regions at H1 formed by epitaxy; para. 0023) on opposite sides (left/right sides) of the first semiconductive nanostructure (channel at H1), and a plurality of second epitaxial structures (drain regions at H2) on opposite sides (left/right sides) of the second semiconductive nanostructure (channel at H2);
forming a first gate (gate lectrode at H1) wrapping around the first semiconductive nanostructure (channel at H1), and a second gate (gate lectrode at H2 wrapping around the second semiconductive nanostructure (channel at H2);
forming third and fourth semiconductive nanostructures (Annotated fig. 12, channel at H3 and H4), the third semiconductive nanostructure (channel at H3) vertically arranged with respect to the second semiconductive nanostructure (channel at H2), and a fourth semiconductive nanostructure (channel at H4) vertically arranged with respect to the third semiconductive nanostructure (channel at H3);
forming a plurality of third epitaxial structures (fig. 4, drain regions at H3) on opposite sides of the third semiconductive nanostructure (channel at H3), and a plurality of fourth epitaxial structures (drain regions at H4) on opposite sides of the fourth semiconductive nanostructure (channel at H4); and
forming a third gate (gate electrode at H3) wrapping around the third semiconductive nanostructure (channel at H3), and a fourth gate (gate electrode at H4) wrapping around the fourth semiconductive nanostructure (channel at H4).
Liaw fails to explicitly teach forming a first power line laterally extending over the first and second gates;
forming third and fourth semiconductive nanostructures over the first power line.
However, Paul teaches forming a first power line (Paul: fig. 2, VSS contact 225B; para. 0024) laterally extending (laterally into the paper) over the first and second gates (Paul: gate structure of pull-up transistor PU1 and pull-down transistor PD1; para. 0019, similar to gate electrode at H1, H2 of Liaw);
forming third and fourth semiconductive nanostructures (Paul: pull-up transistor PU2, pull-down transistor PD2; para. 0019, similar to channel at H3, H4 of Liaw) over the first power line (Paul: 225B).
Paul and Liaw are considered to be analogous to the claimed invention because they are in the same field of SRAM devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the first power line as taught by Paul.
Doing so would realize an interconnect structure to reduce the cell area that allows smaller devices to be fabricated (Paul: para. 0003).
Regarding claim 12, Liaw in view of Paul teaches the method of claim 11, further comprising:
forming a cross coupling line (Paul: fig. 2, cross-connect line 205A, 205B; para. 0022) of a static random access memory cell (Paul: two port SRAM cell; para. 0001) over the first and second gates (Paul: PU1/PD1) and at a same level height as the first power line (Paul: 225B).
Regarding claim 13, Liaw in view of Paul teaches the method of claim 11, further comprising:
before forming the third and fourth semiconductive nanostructures (Paul: fig. 2, PU2/PD2), forming a second power line (Paul: VDD contact 230B; para. 0024) laterally extending (laterally into the paper) over the first and second gates (Paul: PU1/PD1).
Regarding claim 14, Liaw in view of Paul teaches the method of claim 13, wherein the second power line (Paul: fig. 2, in an alternative consideration, cross-connect line 250B; para. 0022) is at a different level height (Paul: horizontal part of 250B is higher than 255B) than the first power line (Paul: 225B) and extends in a direction (horizontal direction) perpendicular to a lengthwise direction (laterally into the paper) of first power line (Paul: 225B).
Regarding claim 15, Liaw in view of Paul teaches the method of claim 13, wherein the second power line (Paul: fig. 2, 230B) is at a different level height than (Paul: 230B higher than 225B) the first power line (Paul: 225B) and extends in a direction in parallel (both parallel into the paper) with a lengthwise direction of first power line (Paul: 225B).
Regarding claim 22, Liaw teaches the method of claim 21 including the third transistor (Annotated fig. 12, PU-2 at H2) and the fifth transistor (PU-2 at H3).
Liaw fails to explicitly teach forming a voltage source line of the SRAM cell, the voltage source line laterally extending in a level height higher than a level height of the third transistor and lower than a level height of the fifth transistor.
However, Paul teaches forming a voltage source line (Paul: fig. 2, VDD contact 230B; para. 0024) of the SRAM cell (Paul: two port SRAM cell; para. 0001), the voltage source line (Paul: 230B) laterally extending (laterally into the paper) in a level height (middle level as H5 of Liaw) higher than a level height of the third transistor (Paul: pull-up transistor PU1 and pull-down transistor PD1; para. 0019, similar to PU-2 at H2 of Liaw) and lower than a level height of the fifth transistor (Paul: pull-up transistor PU2, pull-down transistor PD2; para. 0019, similar to PU-2 at H3 of Liaw).
Paul and Liaw are considered to be analogous to the claimed invention because they are in the same field of SRAM devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add forming a voltage source line as taught by Paul.
Doing so would realize an interconnect structure to reduce the cell area that allows smaller devices to be fabricated (Paul: para. 0003).
Regarding claim 23, Liaw teaches the method of claim 21 including the third transistor (Annotated fig. 12, PU-2 at H2) and the fifth transistor (PU-2 at H3).
Liaw fails to explicitly teach forming a ground line of the SRAM cell, the ground line laterally extending in a level height higher than a level height of the third transistor and lower than a level height of the fifth transistor.
However, Paul teaches forming a ground line (Paul: fig. 2, VSS contact 225B; para. 0024) of the SRAM cell (Paul: two port SRAM cell; para. 0001), the ground line (Paul: 225B) laterally extending (laterally into the paper) in a level height (middle level as H5 of Liaw) higher than a level height of the third transistor (Paul: pull-up transistor PU1 and pull-down transistor PD1; para. 0019, similar to PU-2 at H2 of Liaw) and lower than a level height of the fifth transistor (Paul: pull-up transistor PU2, pull-down transistor PD2; para. 0019, similar to PU-2 at H3 of Liaw).
Paul and Liaw are considered to be analogous to the claimed invention because they are in the same field of SRAM devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add forming a ground line as taught by Paul.
Doing so would realize an interconnect structure to reduce the cell area that allows smaller devices to be fabricated (Paul: para. 0003).
Regarding claim 24, Liaw in view of Paul teaches the method of claim 23, further comprising:
forming a cross coupling line (Paul: fig. 2, cross-connect line 205A, 205B; para. 0022) of the dual port SRAM cell (Paul: two port SRAM cell; para. 0001), the cross coupling line (Paul: 205A, 205B) laterally extending (Paul: 205A laterally extend overlaps with 255B) in the same level height as the ground line (Paul: 255B).
Claims 8 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Xie et al. (US 20230345690).
Regarding claim 8, Liaw teaches the method of claim 1 including the first pull-up and first pass-gate transistors (Annotated fig. 12, PU-1, PG-1 at H1).
Liaw fails to teach forming a complementary bit line of the dual port SRAM cell, the complementary bit line laterally extending between the substrate and the first pull-up and first pass-gate transistors.
However, Xie teaches forming a complementary bit line (Xie: fig. 19A, second bit line 721; para. 0053) of the dual port SRAM cell (Xie: SRAM device; abstract), the complementary bit line (Xie: 721) laterally extending (horizontal direction) between the substrate (Xie: back-of-the-line (BEOL) layers 803; para. 0052, similar to 20 of Liaw) and the first pull-up and first pass-gate transistors (Xie: first PU transistor PU1, first PG transistor PG1; para. 0029, similar to PU-1, PG-1 at H1 or below of Liaw).
Xie and Liaw are considered to be analogous to the claimed invention because they are in the same field of SRAM devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a complementary bit line as taught by Xie.
Doing so would realize a bit line below the transistor to reduce the cell area without requiring fundamental change in the current fabrication processes (Xie: para. 0003).
Regarding claim 25, Liaw teaches the method of claim 21 including the first transistor (Annotated fig. 12, PG-1 at H1)
Liaw fails to teach forming a complementary bit line of the SRAM cell, the complementary bit line laterally extending in a level height below a level height of the first transistor.
However, Xie teaches forming a complementary bit line (Xie: fig. 19A, second bit line 721; para. 0053) of the SRAM cell (Xie: SRAM device; abstract), the complementary bit line (Xie: 721) laterally extending (horizontal direction) in a level height (bottom level) below a level height of the first transistor (Xie: first PG transistor PG1; para. 0024, similar to PG-1 at H1 or below of Liaw).
Xie and Liaw are considered to be analogous to the claimed invention because they are in the same field of SRAM devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a complementary bit line as taught by Xie.
Doing so would realize a bit line below the transistor to reduce the cell area without requiring fundamental change in the current fabrication processes (Xie: para. 0003).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818