DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 05/11/2026. Claims 6, and 8-13 are amended.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al (US 20070075317 A1, hereafter Kato) in view of Pawlak (US 20190088680 A1, hereafter Pawlak) and Schwan et al (US 20040241917 A1, hereafter Schwan).
Regarding claim 1, Kato teaches: A method of making a semiconductor device (Kato figs 3-13B, ¶0022, 0056-0061, 0075-0077), the method comprising:
manufacturing a bias layer (Kato 33, ¶0057, applicant discloses suitable materials for a bias layer includes undoped semiconductor materials, spec ¶0029, MPEP 2144.06) over a buried oxide layer (Kato 32, ¶0066)(Kato fig 8B, ¶0066);
growing a layer of semiconductor material (Kato 35, ¶0057, 0074) over the bias layer (Kato fig 3B, ¶0057);
forming a transistor (Kato 42, 43a, 43b) in the layer of semiconductor material (Kato ¶0075-0076, fig 11B, 12B), wherein the bias layer is between the transistor and a substrate (Kato 31)(Kato fig 11B, 12B);
forming a first deep trench isolation structure (DTI)(Kato 36, 37, 56, ¶0059-0061) extending through the layer of semiconductor material and contacting the substrate (Kato ¶0059-0061, fig 4B, 13B);
forming a first bias contact (Kato 45a, ¶0077) electrically connecting to the bias layer (Kato fig 13B).
Kato does not teach: forming a first bias contact extending through the layer of the semiconductor material; and
forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.
Pawlak, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a first bias contact (Pawlak 162, ¶0067, fig 7) extending through a layer of a semiconductor material (Pawlak 144) and electrically connecting to a bias layer (Pawlak 142, ¶0067)(Pawlak fig 7, ¶0067).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato, such that the first bias contact is formed to extend through the layer of semiconductor material, as taught by Pawlak, in order to provide a direct vertical electrical connection to the bias layer (Pawlak ¶0067), thereby eliminating a need for mesa-edge access and/or improving contact placement flexibility.
Kato in view of Pawlak does not teach: forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.
Pawlak further teaches: forming a contact (Pawlak 161, ¶0067) to contact a substrate (Pawlak 101, at least via 102), wherein the contact is separated from the bias layer (Pawlak 142)(Pawlak fig 7, ¶0068, 161 is at least separated from 142 by 164).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak to include forming a contact to contact the substrate, separated from the bias layer, as taught by Pawlak, in order to control the substrate potential independently from the bias layer (Kato ¶0051, Pawlak ¶0067-0068), thereby improving threshold voltage.
Kato in view of Pawlak does not explicitly teach: the contact extending through the DTI.
Schwan, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a contact (Schwan 213, ¶0040) extending through a DTI (Schwan 208A, ¶0034) to contact a substrate (Schwan 201)(Schwan fig 2e, ¶0040).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak, such that the contact extends through the DTI, in order to utilize existing isolation structures (Schwan ¶0034, 0040), thereby avoiding additional openings through the layer of semiconductor material, and/or eliminating a need for a separate isolation layer, thereby eliminating a process step (Schwan ¶0014, 0053).
Regarding claim 16, Kato teaches: A method of making a semiconductor device (Kato figs 3-13B, ¶0022, 0056-0061, 0075-0077), the method comprising:
manufacturing a bias layer (Kato 33, ¶0057, applicant discloses suitable materials for a bias layer includes undoped semiconductor materials, spec ¶0029, MPEP 2144.06) over a buried oxide layer (Kato 32, ¶0066)(Kato fig 8B, ¶0066);
growing a layer of semiconductor material (Kato 35, ¶0057, 0074) over the bias layer (Kato fig 3B, ¶0057);
forming a transistor (Kato 42, 43a, 43b) in the layer of semiconductor material (Kato ¶0075-0076, fig 11B, 12B), wherein the bias layer is between the transistor and a substrate (Kato 31)(Kato fig 11B, 12B);
forming a first deep trench isolation structure (DTI)(Kato 36, 37, 56, ¶0059-0061) extending through the layer of semiconductor material and contacting the substrate (Kato ¶0059-0061, fig 4B, 13B).
Kato does not explicitly teach: forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.
Pawlak, in the same field of endeavor of semiconductor device manufacturing, teaches:
forming a contact (Pawlak 161, ¶0067) to contact a substrate (Pawlak 101, at least via 102), wherein the contact is separated from the bias layer (Pawlak 142)(Pawlak fig 7, ¶0068, 161 is at least separated from 142 by 164).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato to include forming a contact to contact the substrate, separated from the bias layer, as taught by Pawlak, in order to control the substrate potential independently from the bias layer (Kato ¶0051, Pawlak ¶0067-0068), thereby improving threshold voltage.
Kato in view of Pawlak does not explicitly teach: the contact extending through the DTI.
Schwan, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a contact (Schwan 213, ¶0040) extending through a DTI (Schwan 208A, ¶0034) to contact a substrate (Schwan 201)(Schwan fig 2e, ¶0040).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak, such that the contact extends through the DTI, in order to utilize existing isolation structures (Schwan ¶0034, 0040), thereby avoiding additional openings through the layer of semiconductor material, and/or eliminating a need for a separate isolation layer, thereby eliminating a process step (Schwan ¶0014, 0053).
Regarding claim 17, Kato in view of Pawlak and Schwan teaches: The method of claim 16, further comprising forming a bias contact (Kato 45a, ¶0077) and electrically connecting to the bias layer (Kato 33)(Kato fig 13B).
Kato does not explicitly teach: forming a bias contact extending through the layer of semiconductor material.
Pawlak further teaches: forming a bias contact (Pawlak 162, ¶0067, fig 7) extending through a layer of a semiconductor material (Pawlak 144) and electrically connecting to a bias layer (Pawlak 142, ¶0067)(Pawlak fig 7, ¶0067).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak and Schwan, such that the bias contact is formed to extend through the layer of semiconductor material, as taught by Pawlak, in order to provide a direct vertical electrical connection to the bias layer (Pawlak ¶0067), thereby eliminating a need for mesa-edge access and/or improving contact placement flexibility.
Regarding claim 18, Kato in view of Pawlak and Schwan teaches: The method of claim 17, wherein forming the bias contact (Kato 45a as modified by Pawlak, similar to Pawlak 162) comprises forming the bias contact on an opposite side of the transistor (Kato 42, 43a, 43b, similar to Pawlak 150) from the contact (Kato as modified to include forming Pawlak 161)(Pawlak fig 7).
Regarding claim 19, Kato in view of Pawlak and Schwan, in at least one embodiment, teaches: The method of claim 17, wherein forming the bias contact (Kato 45b as modified by Pawlak) comprises forming the bias contact on a same side of the transistor (Kato 42, 43a, 43b, similar to Pawlak 150) as the contact (Kato as modified to include forming Pawlak 161)(Pawlak fig 7, Kato fig 13B, Kato shows contacts 45a and 45b on opposites sides of the transistor; in at least on embodiment, 45b is on the same side as the DTI through which the contact is formed; further, see MPEP 2144.04).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kato et al (US 20070075317 A1, hereafter Kato) in view of Pawlak (US 20190088680 A1, hereafter Pawlak) and Schwan et al (US 20040241917 A1, hereafter Schwan), as applied to claims 1 or 17 above, and further in view of Gonzalez et al (US 20040041265 A1, hereafter Gonzalez).
Regarding claim 2, Kato in view of Pawlak and Schwan teaches: The method of claim 1.
Kato in view of Pawlak and Schwan does explicitly not teach: further comprising manufacturing a second bias layer over the buried oxide layer.
Kato further teaches: forming multiple DTIs (Kato 36, 37, 56, ¶0059-0061) that divide a bias layer (Kato 33) into separate regions (Kato fig 4A-5B, ¶0059, 0061).
Gonzalez, in the same field of endeavor of semiconductor device manufacturing, teaches: manufacturing a second bias layer (Gonzalez 115, ¶0008, 0025-0027, multiple, each connected to a different voltage source VBB1, VBB2) over a buried oxide layer (Gonzalez 111, ¶0025)(Gonzalez fig 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak and Schwan such that “a second bias layer over the buried oxide layer” is manufactured, in order to individually select bias voltages for different transistors on a device, thereby improving threshold voltage control amongst transistors (Gonzalez ¶0026, 0053).
Allowable Subject Matter
Claims 6-15 are allowable.
Claims 3-5 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein manufacturing the second bias layer comprises manufacturing the second bias layer between the bias layer and the DTI. (Applicant ¶0100, fig 4).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 3 as a whole can be met.
Regarding claim 4, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein manufacturing the bias layer comprises manufacturing the bias layer between the second bias layer and the DTI. (Applicant ¶0100, fig 4).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 4 as a whole can be met.
Regarding claim 5, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
further comprising forming a second bias contact extending through the layer of the semiconductor material and electrically connecting to the second bias layer. (Applicant ¶0100, fig 4).
Kato further teaches: multiple bias contacts (Kato 45a, 45b, fig 13B).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 5 as a whole can be met.
Regarding claim 6, it is allowable primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
forming a second bias contact extending through the layer of semiconductor material and electrically connecting to the second bias layer. (Applicant ¶0100, fig 4).
Kato further teaches: multiple bias contacts (Kato 45a, 45b, fig 13B).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 6 as a whole can be met.
Regarding claims 7-15, the dependent claims are allowable for their dependency to claim 6.
Regarding claim 20, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein the second bias layer is between the bias layer and the contact. (Applicant ¶0100, fig 4).
Gonzalez et al (US 20040041265 A1, hereafter Gonzalez) teaches: manufacturing a second bias layer (Gonzalez 115, ¶0008, 0025-0027, multiple, each connected to a different voltage source VBB1, VBB2) over a buried oxide layer (Gonzalez 111, ¶0025)(Gonzalez fig 1).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 20 as a whole can be met.
Response to Arguments
Applicant's arguments filed 05/11/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 16-19, the applicant alleges at page 6:
Claim 1 recites "manufacturing a bias layer over a buried oxide layer." The Office interpreted element 33 of Kato as corresponding to the recited bias layer; and element 32 of Kato as corresponding to the recited buried oxide layer. (Office Action at page 3). Kato states "single-crystal semiconductor layers 33 and 35 are thermally oxidized, thereby forming surface oxide films 32 a and 32 c respectively arranged on the upper and lower surfaces of the cavities 57 a between the single-crystal semiconductor substrate 31 and single-crystal semiconductor layer 33 and forming buried oxide films 34 in the cavities 57 b between the single- crystal semiconductor layers 33 and 35." (Kato at paragraph 0066). Kato explicitly states that the element 32 is formed by thermal processing of element 33. Therefore, Kato cannot reasonably be interpreted as teaching or suggest that element 33 is manufactured over element 32 because element 32 does not exist when element 33 is manufactured.
Examiner’s response:
The Examiner respectfully disagrees. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., temporal and/or sequential order of formation) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim 1 recites “manufacturing a bias layer over a buried oxide layer.” The claim does not recite a separate, antecedent step of forming a buried oxide layer, nor any other limitation regarding the formation of, manufacture of, and/or relationship between a bias layer and a buried oxide layer, beyond a spatial relationship. Under a broadest reasonable interpretation, any series of manufacturing processes that results in “a bias layer over a buried oxide layer” meets this limitation, regardless of the order in which the two layers are formed.
Kato discloses the claimed spatial relationship: a bias layer (Kato 33) spatially located over a buried oxide layer (Kato 32)(Kato fig 8B), and a method of manufacturing that results in the aforementioned spatial relationship (Kato ¶0066). Therefore, Kato teaches the claimed limitation of “manufacturing a bias layer over a buried oxide layer”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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