DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 9, it recites the limitation "the semiconductor layer" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of compact prosecution, the Examiner interprets “the semiconductor layer” to mean “the layer of semiconductor material”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al (US 20070075317 A1, hereafter Kato) in view of Pawlak (US 20190088680 A1, hereafter Pawlak) and Schwan et al (US 20040241917 A1, hereafter Schwan).
Regarding claim 1, Kato teaches: A method of making a semiconductor device (Kato figs 3-13B, ¶0022, 0056-0061, 0075-0077), the method comprising:
manufacturing a bias layer (Kato 33, ¶0057, applicant discloses suitable materials for a bias layer includes undoped semiconductor materials, spec ¶0029, MPEP 2144.06) over a buried oxide layer (Kato 32, ¶0066)(Kato fig 8B, ¶0066);
growing a layer of semiconductor material (Kato 35, ¶0057, 0074) over the bias layer (Kato fig 3B, ¶0057);
forming a transistor (Kato 42, 43a, 43b) in the layer of semiconductor material (Kato ¶0075-0076, fig 11B, 12B), wherein the bias layer is between the transistor and a substrate (Kato 31)(Kato fig 11B, 12B);
forming a first deep trench isolation structure (DTI) (Kato 36, 37, 56, ¶0059-0061) extending through the layer of semiconductor material and contacting the substrate (Kato ¶0059-0061, fig 4B, 13B);
forming a first bias contact (Kato 45a, ¶0077) electrically connecting to the bias layer (Kato fig 13B).
Kato does not teach: forming a first bias contact extending through the layer of the semiconductor material; and
forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.
Pawlak, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a first bias contact (Pawlak 162, ¶0067, fig 7) extending through a layer of a semiconductor material (Pawlak 144) and electrically connecting to a bias layer (Pawlak 142, ¶0067)(Pawlak fig 7, ¶0067).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato, such that the first bias contact is formed to extend through the layer of semiconductor material, as taught by Pawlak, in order to provide a direct vertical electrical connection to the bias layer (Pawlak ¶0067), thereby eliminating a need for mesa-edge access and/or improving contact placement flexibility.
Kato in view of Pawlak does not teach: forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.
Pawlak further teaches: forming a contact (Pawlak 161, ¶0067) to contact a substrate (Pawlak 101, at least via 102), wherein the contact is separated from the bias layer (Pawlak 142)(Pawlak fig 7, ¶0068, 161 is at least separated from 142 by 164).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak to include forming a contact to contact the substrate, separated from the bias layer, as taught by Pawlak, in order to control the substrate potential independently from the bias layer (Kato ¶0051, Pawlak ¶0067-0068), thereby improving threshold voltage.
Kato in view of Pawlak does not explicitly teach: the contact extending through the DTI.
Schwan, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a contact (Schwan 213, ¶0040) extending through a DTI (Schwan 208A, ¶0034) to contact a substrate (Schwan 201)(Schwan fig 2e, ¶0040).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak, such that the contact extends through the DTI, in order to utilize existing isolation structures (Schwan ¶0034, 0040), thereby avoiding additional openings through the layer of semiconductor material, and/or eliminating a need for a separate isolation layer, thereby eliminating a process step (Schwan ¶0014, 0053).
Regarding claim 16, Kato teaches: A method of making a semiconductor device (Kato figs 3-13B, ¶0022, 0056-0061, 0075-0077), the method comprising:
manufacturing a bias layer (Kato 33, ¶0057, applicant discloses suitable materials for a bias layer includes undoped semiconductor materials, spec ¶0029, MPEP 2144.06) over a buried oxide layer (Kato 32, ¶0066)(Kato fig 8B, ¶0066);
growing a layer of semiconductor material (Kato 35, ¶0057, 0074) over the bias layer (Kato fig 3B, ¶0057);
forming a transistor (Kato 42, 43a, 43b) in the layer of semiconductor material (Kato ¶0075-0076, fig 11B, 12B), wherein the bias layer is between the transistor and a substrate (Kato 31)(Kato fig 11B, 12B);
forming a first deep trench isolation structure (DTI) (Kato 36, 37, 56, ¶0059-0061) extending through the layer of semiconductor material and contacting the substrate (Kato ¶0059-0061, fig 4B, 13B).
Kato does not explicitly teach: forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer.
Pawlak, in the same field of endeavor of semiconductor device manufacturing, teaches:
forming a contact (Pawlak 161, ¶0067) to contact a substrate (Pawlak 101, at least via 102), wherein the contact is separated from the bias layer (Pawlak 142)(Pawlak fig 7, ¶0068, 161 is at least separated from 142 by 164).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato to include forming a contact to contact the substrate, separated from the bias layer, as taught by Pawlak, in order to control the substrate potential independently from the bias layer (Kato ¶0051, Pawlak ¶0067-0068), thereby improving threshold voltage.
Kato in view of Pawlak does not explicitly teach: the contact extending through the DTI.
Schwan, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a contact (Schwan 213, ¶0040) extending through a DTI (Schwan 208A, ¶0034) to contact a substrate (Schwan 201)(Schwan fig 2e, ¶0040).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak, such that the contact extends through the DTI, in order to utilize existing isolation structures (Schwan ¶0034, 0040), thereby avoiding additional openings through the layer of semiconductor material, and/or eliminating a need for a separate isolation layer, thereby eliminating a process step (Schwan ¶0014, 0053).
Regarding claim 17, Kato in view of Pawlak and Schwan teaches: The method of claim 16, further comprising forming a bias contact (Kato 45a, ¶0077) and electrically connecting to the bias layer (Kato 33)(Kato fig 13B).
Kato does not explicitly teach: forming a bias contact extending through the layer of semiconductor material.
Pawlak further teaches: forming a bias contact (Pawlak 162, ¶0067, fig 7) extending through a layer of a semiconductor material (Pawlak 144) and electrically connecting to a bias layer (Pawlak 142, ¶0067)(Pawlak fig 7, ¶0067).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak and Schwan, such that the bias contact is formed to extend through the layer of semiconductor material, as taught by Pawlak, in order to provide a direct vertical electrical connection to the bias layer (Pawlak ¶0067), thereby eliminating a need for mesa-edge access and/or improving contact placement flexibility.
Regarding claim 18, Kato in view of Pawlak and Schwan teaches: The method of claim 17, wherein forming the bias contact (Kato 45a as modified by Pawlak, similar to Pawlak 162) comprises forming the bias contact on an opposite side of the transistor (Kato 42, 43a, 43b, similar to Pawlak 150) from the contact (Kato as modified to include forming Pawlak 161)(Pawlak fig 7).
Regarding claim 19, Kato in view of Pawlak and Schwan, in at least one embodiment, teaches: The method of claim 17, wherein forming the bias contact (Kato 45b as modified by Pawlak) comprises forming the bias contact on a same side of the transistor (Kato 42, 43a, 43b, similar to Pawlak 150) as the contact (Kato as modified to include forming Pawlak 161)(Pawlak fig 7, Kato fig 13B, Kato shows contacts 45a and 45b on opposites sides of the transistor; in at least on embodiment, 45b is on the same side as the DTI through which the contact is formed; further, see MPEP 2144.04).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kato et al (US 20070075317 A1, hereafter Kato) in view of Pawlak (US 20190088680 A1, hereafter Pawlak) and Schwan et al (US 20040241917 A1, hereafter Schwan), as applied to claims 1 or 17 above, and further in view of Gonzalez et al (US 20040041265 A1, hereafter Gonzalez).
Regarding claim 2, Kato in view of Pawlak and Schwan teaches: The method of claim 1.
Kato in view of Pawlak and Schwan does explicitly not teach: further comprising manufacturing a second bias layer over the buried oxide layer.
Kato further teaches: forming multiple DTIs (Kato 36, 37, 56, ¶0059-0061) that divide a bias layer (Kato 33) into separate regions (Kato fig 4A-5B, ¶0059, 0061).
Gonzalez, in the same field of endeavor of semiconductor device manufacturing, teaches: manufacturing a second bias layer (Gonzalez 115, ¶0008, 0025-0027, multiple, each connected to a different voltage source VBB1, VBB2) over a buried oxide layer (Gonzalez 111, ¶0025)(Gonzalez fig 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak and Schwan such that “a second bias layer over the buried oxide layer” is manufactured, in order to individually select bias voltages for different transistors on a device, thereby improving threshold voltage control amongst transistors (Gonzalez ¶0026, 0053).
Claims 6, 7, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al (US 20070075317 A1, hereafter Kato) in view of Pawlak (US 20190088680 A1, hereafter Pawlak).
Regarding claim 6, Kato teaches: A method of making a semiconductor device (Kato figs 3-13B, ¶0022, 0056-0061, 0075-0077), the method comprising:
manufacturing a bias layer (Kato 33, ¶0057, applicant discloses suitable materials for a bias layer includes undoped semiconductor materials, spec ¶0029, MPEP 2144.06) over a buried oxide layer (Kato 32, ¶0066)(Kato fig 8B, ¶0066);
growing a layer of semiconductor material (Kato 35, ¶0057, 0074) over the bias layer (Kato fig 3B, ¶0057);
forming a transistor (Kato 42, 43a, 43b) in the layer of semiconductor material (Kato ¶0075-0076, fig 11B, 12B), wherein the bias layer is between the transistor and a substrate (Kato 31)(Kato fig 11B, 12B);
forming a first deep trench isolation structure (DTI) (Kato 36, 37, 56, ¶0059-0061) extending through the layer of semiconductor material and contacting the substrate (Kato ¶0059-0061, fig 4B, 13B); and
forming a first bias contact (Kato 45a, ¶0077) electrically connecting to the bias layer (Kato fig 13B).
Kato does not explicitly teach: forming a first bias contact extending through the layer of semiconductor material and electrically connecting to the bias layer.
Pawlak, in the same field of endeavor of semiconductor device manufacturing, teaches: forming a first bias contact (Pawlak 162, ¶0067, fig 7) extending through a layer of a semiconductor material (Pawlak 144) and electrically connecting to a bias layer (Pawlak 142, ¶0067)(Pawlak fig 7, ¶0067).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato, such that the first bias contact is formed to extend through the layer of semiconductor material, as taught by Pawlak, in order to provide a direct vertical electrical connection to the bias layer (Pawlak ¶0067), thereby eliminating a need for mesa-edge access and/or improving contact placement flexibility.
Regarding claim 7, Kato in view of Pawlak teaches: The method of claim 6, further comprising forming a dielectric layer (Kato 34, ¶0027, 0066) over the bias layer (Kato 33), wherein growing the layer of semiconductor material (Kato 35) comprises growing the layer of semiconductor material over the dielectric layer (Kato ¶0066-0068, fig 7B, 8B, 13B).
Regarding claim 15, Kato in view of Pawlak teaches: The method of claim 6, wherein forming the transistor (Kato 42, 43a, 43b) comprises forming a well region (Kato 43a, 43b, ¶0076, under a broadest reasonable interpretation, a doped region formed in a semiconductor layer is a well region) in the layer of semiconductor material (Kato 35), wherein the well region partially overlaps the bias layer (Kato 33)(Kato ¶0076, fig 12B).
Claim 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kato et al (US 20070075317 A1, hereafter Kato) in view of Pawlak (US 20190088680 A1, hereafter Pawlak), as applied to claim 6 above, and further in view of Gonzalez et al (US 20040041265 A1, hereafter Gonzalez).
Regarding claim 8, Kato in view of Pawlak teaches: The method of claim 6.
Kato in view of Pawlak does explicitly not teach: further comprising manufacturing a second bias layer over the buried oxide layer, wherein the second bias layer is spaced from the bias layer in a direction parallel to a top surface of the substrate.
Kato further teaches: forming multiple DTIs (Kato 36, 37, 56, ¶0059-0061) that divide a bias layer (Kato 33) into separate regions (Kato fig 4A-5B, ¶0059, 0061), wherein the regions are spaced in a direction parallel to a top surface of the substrate (Kato 31)(Kato fig 4A-5B).
Gonzalez, in the same field of endeavor of semiconductor device manufacturing, teaches:
manufacturing a second bias layer (Gonzalez 115, ¶0008, 0025-0027, multiple, each connected to a different voltage source VBB1, VBB2) over a buried oxide layer (Gonzalez 111, ¶0025)(Gonzalez fig 1), wherein the second bias layer is spaced from the bias layer in a direction parallel to a top surface of a substrate (Gonzalez 105)(Gonzalez fig 1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of Kato in view of Pawlak such that “a second bias layer over the buried oxide layer, wherein the second bias layer is spaced from the bias layer in a direction parallel to a top surface of the substrate” is manufactured, in order to individually select bias voltages for different transistors on a device, thereby improving threshold voltage control amongst transistors (Gonzalez ¶0026, 0053).
Regarding claim 12, Kato in view of Pawlak and Gonzalez teaches: The method of claim 8, wherein forming the first DTI (Kato 36, 37, 56) comprises forming the first DTI between the bias layer (Kato 33 as modified by Gonzalez) and the second bias layer (Kato 33 as modified by Gonzalez)(Kato fig 13B).
Allowable Subject Matter
Claims 3-5, 9-11, 13, 14, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein manufacturing the second bias layer comprises manufacturing the second bias layer between the bias layer and the DTI. (Applicant ¶0100, fig 4).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 3 as a whole can be met.
Regarding claim 4, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein manufacturing the bias layer comprises manufacturing the bias layer between the second bias layer and the DTI. (Applicant ¶0100, fig 4).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 4 as a whole can be met.
Regarding claim 5, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
further comprising forming a second bias contact extending through the layer of the semiconductor material and electrically connecting to the second bias layer. (Applicant ¶0100, fig 4).
Kato further teaches: multiple bias contacts (Kato 45a, 45b, fig 13B).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 5 as a whole can be met.
Regarding claim 9, it is allowable, not withstand above rejection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
further comprising forming a second bias contact extending through the semiconductor layer (as best understood to mean “the layer of the semiconductor material”) and electrically connecting to the second bias layer. (Applicant ¶0100, fig 4).
Kato further teaches: multiple bias contacts (Kato 45a, 45b, fig 13B).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 9 as a whole can be met.
Regarding claims 10 and 11, the dependent claims are allowable for their dependency to claim 9.
Regarding claim 13, it is allowable, not withstand above rejection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
further comprising forming a second DTI between the bias layer and the second bias layer. (Applicant ¶0100).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 13 as a whole can be met.
Regarding claim 14, the dependent claim is allowable for its dependency to claim 13.
Regarding claim 20, it is allowable, not withstand above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein the second bias layer is between the bias layer and the contact. (Applicant ¶0100, fig 4).
Gonzalez et al (US 20040041265 A1, hereafter Gonzalez) teaches: manufacturing a second bias layer (Gonzalez 115, ¶0008, 0025-0027, multiple, each connected to a different voltage source VBB1, VBB2) over a buried oxide layer (Gonzalez 111, ¶0025)(Gonzalez fig 1).
Kato in view of Pawlak, Schwan, and Gonzales in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Kato, Pawlak, Schwan, Gonzalez, or any other prior arts of record so that all of limitations of claim 20 as a whole can be met.
Conclusion
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818