Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s cancellation of claim 3 is acknowledged.
Applicant’s addition of claim 21 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, and 4 - 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20180294331 A1 hereinafter Cho in view of US 20140001561 A1 hereinafter Cheng and in further view of US 20200105889 A1 hereinafter Liaw.
For claim 1, Cho teaches a semiconductor device (Cho, fig. 2) comprising circuit cells having transistors (fig. 2 numeral 100), wherein each of the transistors comprises: nanostructures vertically stacked from each other in a Z-direction (fig. 2 numeral 150); a gate structure wrapping around the nanostructures and extending in the Y-direction (fig. 1 shows the nanostructures being wrapped by the gate structure shown by device region DR and active regions FA wrapping around the nanostructures NSS; fig. 2 numeral 150; Par. [0037]); source/drain features on opposite sides of the gate structure in an X-direction (fig. 2 numeral 162A); silicide features over and in contact with the source drain features, wherein the silicide features extend lower than bottom surfaces of the topmost nanostructures of the nanostructures (fig. 2 numeral 162B; Par [0042]); and source/drain contacts over and in contact with the silicide features (fig. 2 numeral 190). Cho is silent regarding the bottom surfaces of the source/drain contacts having a V-shape in an X-Z cross-sectional view. Cho does teach the contacts having a tapered shape similar to a V in an X-Z cross-sectional view (fig. 2 numeral 190). Cho is silent regarding at least one of a top surface of the silicide features has a lowest point lower than top surfaces of the topmost nanostructures of the nanostructures and higher than the bottom surfaces of the topmost nanostructures of the nanostructures in a cross-sectional view.
Cheng teaches a circuit cell having transistors (Cheng, fig. 6) having source/drain contacts (fig. 6 numeral 602) with a V-shape bottom surface (fig. 6 shows contacts have a V-shape at the bottom surface) and the source/drain contact is in contact with a silicide layer (fig. 6 numeral 502).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the V-shape contact in Cheng with the source/drain regions in Cho in order to reduce resistance in the device for better performance (Cheng, Par. [0004]) and increase electron mobility (Par. [0037]). Cho and Cheng are silent regarding at least one of a top surface of the silicide features has a lowest point lower than top surfaces of the topmost nanostructures of the nanostructures and higher than the bottom surfaces of the topmost nanostructures of the nanostructures in a cross-sectional view.
Liaw teaches a semiconductor device (Liaw, fig. 37) comprising nanostructures stacked vertically (fig. 37 numeral 210A), source and drain features on opposite sides of the gate structure in an X-direction (fig. 37 numeral 260) and a silicide feature over and in contact with the source and drain features (fig. 37 numeral 240). Liaw also teaches the silicide feature having at least one top surface at a lower point than top surfaces of the topmost nanostructures of the nanostructures and higher than the bottom surfaces of the topmost nanostructures of the nanostructures in a cross-sectional view (fig. 37 shows silicide feature 240 having at least one top surface lower than the top surface of the topmost nanostructure 210A and that the silicide feature extends as to have a top surface that is higher than the bottom surfaces of the topmost nanostructure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the extended structure of the silicide feature in Liaw with the shape and location of the silicide feature in Cho and Cheng in order to reduce parasitic resistance and increase performance of the device (Liaw, Par. [0044], Par. [0057]; Par. [0072]).
For claim 2, Cho, Cheng, and Liaw teach all of claim 1. Cheng also teaches the silicide features having a V-shape in a X-Z cross-sectional view (Cheng, fig. 6 numeral 502).
For claim 3, Cho, Cheng, and Liaw teach all of claim 2. Cho also teaches each of the top surfaces of the silicide features has a lowest point lower than top surfaces of the topmost nanostructures of the nanostructures and higher than the bottom surface of the topmost nanostructures of the nanostructures (Cho, fig. 2 shows silicide feature 162B having topmost surfaces lower than the top surfaces of the topmost nanostructure N3 and having a higher top surface than the bottom surface of the topmost nanostructure N3).
For claim 4, Cho, Cheng, and Liaw teach all of claim 2. Cho also teaches the silicide features (Cho, fig. 2 numeral 162B) having a highest point higher than top surfaces of the topmost nanostructures of the nanostructures (fig. 2 numeral N3).
For claim 5, Cho, Cheng, and Liaw teach all of claim 1. Cho also teaches the top surfaces of the source/drain contacts being substantially level with top surfaces of the gate structure (Cho, fig. 2 numeral 190 shows the contacts as being level with top surfaces of the gate structures 174; Par. [0040]; Par. [0148]).
For claim 6, Cho, Cheng, and Liaw teach all of claim 1. Cheng also teaches a first source/drain contact (Cheng, fig. 12 numeral 602) over N-type source/drain features of the source/drain features (fig. 12 numeral 112; Par. [0026]); and second source/drain contacts (fig. 12 numeral 602) over the P-type source/drain features of the source drain features (fig. 12 numeral 114), wherein bottom surfaces of the first source/drain contacts are lower than bottom surfaces of the second source/drain contacts (fig. 12 shows source/drain contacts 602 having a lower bottom surface in the region contacting the N-type source/drain features 112).
For claim 7, Cho, Cheng, and Liaw teach all of claim 1. Cho also teaches dielectric layers on sidewalls of the source/drain contacts (Cho, fig. 2 numeral 138).
For claim 8, Cho, Cheng, and Liaw teach all of claim 1. Cho also teaches dielectric structures on opposite sides of the gate structures in the Y-direction, wherein one of the source/drain contacts is in contact with one of the dielectric structures (Cho, fig. 2 numeral 172 show dielectric structures in contact with source/drain contacts 190; fig. 1 shows the nanostructures NSS surrounded in the Y direction by the insulating layers).
For claim 9, Cho, Cheng, and Liaw teach all of claim 9. Cho also teaches bottom dielectric layers under the source/drain features (Cho, fig. 2 numeral 145; Par. [0113]).
For claim 10, Cho, Cheng, and Liaw teach all of claim 8. Cho also teaches the thickness of the bottom dielectric layers is in a range from about 2 nm to about 10 nm (Cho, Par. [0113 - 0115]).
Claim(s) 11, and 13 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20180294331 A1 hereinafter Cho in view of US 20140001561 A1 hereinafter Cheng and in further view of US 20200044087 A1 hereinafter Guha.
For claim 11, Cho teaches a semiconductor device, comprising: a substrate (Cho, fig. 2 numeral 102); first nanostructures vertically stacked over the substrate from each other in a Z-direction; second nanostructures vertically stacked over the substrate from each other in the Z-direction (fig. 2 numeral 150); a gate structure (fig. 1 – 3 numeral 150; Par. [0037]) comprising a gate electrode (fig. 19 numeral 150M; fig. 2 numeral 150M) wrapping around the first nanostructures and the second nanostructures and extending in the Y-direction; N-type source/drain features attached to the first nanostructures in an X-direction; P-type source/drain features attached to the second nanostructures in the X direction (fig. 3 numeral FA; Par. [0028] teaches the active regions FA including a p-type and/or n-type impurity source/drain feature; fig. 2 shows the nanostructures 150 attached to the N-type and P-type features in FA in the X-direction by source/drain layer 162A); silicide features over and in contact with the N-type source/drain features and the P-type source/drain features (fig. 2 numeral 162B), wherein the lowest points of bottom surfaces of the silicide features are lower than bottom surfaces of the topmost nanostructures of the first nanostructures and the second nanostructures (fig. 2 shows silicide feature 162B having a lowest point of the bottom surface being lower than the bottom surface of the topmost nanostructure of the first and second nanostructures 150M); and source/drain contacts over and in contact with the silicide features (fig. 2 numeral 190).
Cho is silent regarding the bottom surfaces of the silicide features having a V-shape in an X-Z cross-sectional view. Cho does teach the silicide features having a tapered shape similar to a V in an X-Z cross-sectional view (fig. 2 numeral 162B). Cho is silent regarding the top surfaces of the source/drain contacts are sustainably level with the top surfaces of the gate electrode. Cho does teach that the gate structure including the gate electrode can be changed into different shapes and sizes (Par. [0038 - 0040]). Cho is silent regarding the top surfaces of the source/drain contacts are sustainably level with the top surfaces of the gate electrode.
Cheng teaches a circuit cell having transistors (Cheng, fig. 6) having a silicide layer with a V-shape (fig. 6 numeral 502).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the V-shape silicide feature in Cheng with the source/drain regions in Cho in order to reduce contact resistance (Cheng, Par. [0037]). Cho and Cheng are silent regarding the top surfaces of the source/drain contacts are sustainably level with the top surfaces of the gate electrode.
Guha teaches a semiconductor device (Guha, fig. 14A) with source/drain features (fig. 14A numeral 360) between gate structures including gate electrodes (fig. 14A numeral 336) and wherein a source/drain contact (fig. 14A numeral 390) is shown to be substantially level with top surfaces of the gate electrode (fig. 14A shows contacts 390 level with the top surfaces of the gate electrode 336).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the level gate electrode and contact in Guha with the gate structures and source/drain structure in Cho and Cheng as Cho teaches the shape and sizes of the gate structures are variable (Cho, Par. [0038 – 0040]) and to assist in depositing other layers on top of the contact layer and the gate electrodes by providing a sustainably flat surface by having the layers level with each other.
For claim 13, Cho, Cheng, and Guha teach all of claim 11. Cheng also teaches each of the source/drain contacts (Cheng, fig. 6 numeral 602) a V-shaped bottom surface in a cross-sectional view (fig. 6 numeral 602; the V-shape is shown to be in two directions that would correspond to the X-Z directions in Cho).
For claim 14, Cho, Cheng, and Guha teach all of claim 11. Cheng also teaches a first source/drain contact (Cheng, fig. 12 numeral 602) is directly over a N-type source/drain feature (fig. 12 numeral 112; Par. [0026]); and second source/drain contacts (fig. 12 numeral 602) over the P-type source/drain features (fig. 12 numeral 114), wherein bottom surfaces of one of the source/drain contacts over the N-type source/drain features is lower than a bottom surface of the source/drain contacts over the P-type source/drain features (fig. 12 shows source/drain contacts 602 having a lower bottom surface in the region contacting the N-type source/drain features 112). Cheng does not explicitly state that the source/drain contact over the P-type source/drain feature comprises a second portion. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the source/drain contacts in Cho, Cheng, and Guha can comprise multiple portions as Cheng teaches the contact plug area comprising multiple sections with different widths (Cheng, fig. 4A numeral 402 and 404) and that the contact plug fills each separate portion (fig. 6 numeral 602) resulting in lower portions filing section 402 and higher portions filing section 404 as shown in figure 4A.
For claim 15, Cho, Cheng, and Guha teach all of claim 15. Cheng also teaches bottom dielectric layers under the N-type source/drain features and the P-type source/drain features (Cheng, fig. 14 numeral 104).
For claim 16, Cho, Cheng, and Guha teach all of claim 11. Cheng also teaches embodiments wherein source/drain features have dielectric layers under the source/drain features (Cheng, fig. 12 numeral 104) and embodiments wherein the source/drain features are in contact with the substrate with no intervening layer (fig. 13 numeral 1302 and 1304 show source/drain features in contact with the substrate 102). Cho, Cheng, and Guha is silent regarding the bottom dielectric layer present under the N-type source layer and the P-type source/drain feature being in contact with the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the source/drain features in Cho, Cheng, and Guha includes embodiments wherein the N-type source/drain feature has a bottom dielectric layer and wherein the P-type source/drain feature is in contact with the substrate as Cheng teaches embodiments with the bottom dielectric layer (Cheng, fig. 12) and without (fig. 13) and Cheng also teaches improving the device’s performance by controlling the total resistance in the device (Cheng, Par. [0004]) while also controlling the length of the channel underneath each gate by increasing or decreasing the size of each source/drain feature (Cheng, Par. [0046]). One would be driven to modify Cheng and Cho to include a bottom dielectric layer underneath the N-type source/drain feature and having the P-type source/drain feature in contact with the substrate to optimize the overall resistance in device, optimize the relative resistance in each source/drain feature, or to optimize the channel length of each area of the device.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20180294331 A1 hereinafter Cho in view of US 20140001561 A1 hereinafter Cheng, in view of US 20200044087 A1 hereinafter Guha, and in further view of US 20200105880 A1 hereinafter Dasgupta.
For claim 12, Cho, Cheng, and Guha teach all of claim 12. Cho does teach the lowest point of the bottom surfaces of the silicide features being lower than the bottom surfaces of the topmost nanostructures (Cho, fig. 2 numeral 162B). Cho, Cheng, and Guha are silent regarding the lowest points of the bottom surface of the silicide features are about 1 nm to about 15 nm lower than the bottom surfaces of the topmost structures.
Dasgupta teaches a device comprising transistors (Dasgupta, fig. 2A) with a silicide layer in a V-shape (fig. 2A numeral 112), and that the depth of the recess that the silicide layer is deposited in (fig. 2A numeral 108C and 110C) is between 10 nm and 25 nm (Par. [0054]) and is variable depending on the desired thickness of the source/drain features (Par. [0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the depth ranges in Dasgupta would include ranges between 1 nm to 15 nm as Dasgupta teaches a similar range and also teaches the depth of the recesses that the silicide layer fills is a result effective variable that can be modified depending on the desired outcome of the device. One would be driven to change the recess depth in order to optimize the electrical resistance and current flow through the transistor (Dasgupta, Par. [0044]) and optimize the surface area contact between the source/drain features and the silicide feature (Dasgupta, Par. [0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the recess depth in Dasgupta with the lower bottom surface of the silicide feature being below the bottom surfaces of the topmost nanostructure in Cho, Cheng, and Guha in order to optimize the electrical resistance and current flow through the transistor (Dasgupta, Par. [0044]) and optimize the surface area contact between the source/drain features and the silicide feature (Dasgupta, Par. [0048]).
Allowable Subject Matter
Claims 17 - 21 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 17’s “…wherein a shortest distance from a first one of the source/drain contacts to the substrate in the Z-direction is greater than a distance from the bottom surfaces of a first one of the topmost nanostructures of the nanostructures to the substrate in the Z-direction and is less than a distance from a top surface of the first one of the topmost nanostructures of the nanostructures to the substrate in the Z-direction”.
Claims 18 – 21 are allowable as being dependent on an allowable base claim.
Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 11have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see pages 5 - 7 of applicants remarks, filed 02/10/2026, with respect to claim 17 have been fully considered and are persuasive. The rejection of claim 17 dated 11/04/2025 has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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