DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on December 2nd, 2025 is acknowledged. By virtue of this election, claims 1 and 10-15 are currently presented in the instant application. Claims 2-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species.
Claim Rejections - 35 USC § 112
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation "a power semiconductor device according to claim 1" in line 2. There is no power semiconductor device in claim 1. As best understood and for examination, this limitation should be --a semiconductor device according to claim 1--.
Claim 15 recites the limitation “configured to convert and output input power.” What is output input power? For the purposes of examination this limitation is understood to be --configured to convert power--.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka et al. (US 2020/0177093 A1; hereinafter Matsuoka) in view of Shimoyama et al. (US 2019/0088577 A1; hereinafter Shimoyama).
With respect to claim 1, Matsuoka discloses a semiconductor device 1 in at least Figs. 1-6 comprising:
a conductor 21P having a plate shape with a first thickness (of 21P in X direction in Fig. 4) (see Figs. 1-5 and paragraphs 35, 38-42, 50);
a module body 20 sealing a portion (21P within 20) of the conductor 21P (see Figs. 1-5 and paragraphs 35, 50, 51, 77);
a semiconductor element 2P sealed in the body and electrically connected to the portion (21P within 20) (see Figs. 1-6 and paragraphs 37-39, 48, 49); and
a terminal 41P bonded (at 11P) to the conductor 21P outside of the module body 20 (see Figs. 1-5 and paragraphs 40, 41, 59, 60, 63-65), wherein
a length (along 21P in Z direction in Fig. 4), along the conductor 21P, from a section 11P where the conductor 21P and the terminal 41P are bonded (at 11P) toward the semiconductor element 2P to the module body 20, is greater than the first thickness (of 21P in X direction in Fig. 4) (see Figs. 1-5 and paragraphs 40, 41, 59, 60, 63-65).
Matsuoka does not explicitly disclose wherein the module body is an insulator.
Shimoyama discloses a semiconductor device in at least Figs. 5-15 wherein a module body MR is an insulator (see Figs. 5-15 and paragraphs 78, 83; note epoxy resin. Also see paragraph 10 of applicant’s original specification and note epoxy resin).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the module body of Matsuoka would be an insulator as taught by Shimoyama because it is well known in the art that such module bodies are made of an insulator to electrically isolate device components (see MPEP 2144 I). It has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill (see MPEP 2144.07).
With respect to claim 10, the combination of Matsuoka and Shimoyama discloses the semiconductor device according to claim 1, further comprising a bonding wire BW connecting the portion (MR covered part of LD) and the semiconductor element CPC (see Shimoyama: Fig. 14 and paragraphs 81, 100, 112, 113).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a bonding wire could connect the portion and the semiconductor device because wire bonding is a well-known electrical interconnection method (see MPEP 2144 I).
With respect to claim 11, the combination of Matsuoka and Shimoyama discloses the semiconductor device according to claim 10, wherein the semiconductor device CPC includes a control section, and the bonding wire BW ties the portion (MR covered part of LD) and the control section (see Shimoyama: Fig. 14 and paragraphs 55, 64, 81, 100, 112, 113; control circuit CLC formed within CPC).
With respect to claim 12, the combination of Matsuoka and Shimoyama discloses the semiconductor device according to claim 1, wherein the section 11P is obtained by laser welding (see Matsuoka: Figs. 1-4 and paragraph 64).
With respect to claim 13, the combination of Matsuoka and Shimoyama discloses the semiconductor device according to claim 1, wherein the semiconductor element 2 includes a reverse conducting insulated gate bipolar transistor (see Figs. 1-4 and paragraphs 44, 45, 112; note freewheeling diode connected antiparallel with the IGBT, i.e., reverse conducting IGBT).
With respect to claim 14, the combination of Matsuoka and Shimoyama discloses the semiconductor device according to claim 1, wherein the semiconductor element 2 contains silicon carbide as a semiconductor (see Matsuoka: Figs. 1-4 and paragraph 112).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuoka et al. (US 2020/0177093 A1; hereinafter Matsuoka) in view of Shimoyama et al. (US 2019/0088577 A1; hereinafter Shimoyama) as applied to claim 1 above, and further in view of Kawashima et al. (JP 2018-073923; hereinafter Kawashima; note IDS dated 09/12/2023 with corresponding translation).
With respect to claim 15, (and in view of the 112 rejection) the combination of Matsuoka and Shimoyama discloses a power conversion device comprising: a main conversion circuit 101 including a semiconductor device 1 according to claim 1, and configured to convert power (see Figs. 1-6, Abstract, and paragraphs 43, 44 and rejection of claim 1 above).
The combination does not explicitly disclose a drive circuit configured to output a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit configured to output a control signal for controlling the drive circuit to the drive circuit.
Kawashima discloses a power conversion device in at least Fig. 15 comprising a drive circuit (of 201) configured to output a drive signal for driving the semiconductor device to the semiconductor device 101; and a control circuit 203 configured to output a control signal for controlling the drive circuit to the drive circuit (of 201) (see Fig. 15 and paragraphs 61-68).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the power conversion device of the combination of Matsuoka and Shimoyama would further comprise a drive circuit configured to output a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit configured to output a control signal for controlling the drive circuit to the drive circuit as taught by Kawashima because it is well known in the art that power conversion devices have drive circuits and control circuits (see MPEP 2144 I).
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference teaches a semiconductor device similar to that of the claimed invention: US 20100140786 A1, US 20110180809 A1, US 20190103344 A1.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893