DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 8 is objected to because of the following informalities: it appears that the claim language “selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to the corresponding cut-gate section is than a first reference value less than a first reference value relative to the second direction” is missing the terminology “less than” or “greater than.”
Therefore Claim 8, for the purposes of examination, is interpreted to mean “selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to the corresponding cut-gate section is less than a first reference value less than a first reference value relative to the second direction.” Appropriate correction is required.
Claim 20 is objected to because of the following informalities: it appears the claim language “a first masking facility configured to fabricate one or more semiconductor masks based on based on the layout diagram” should be written as “a first masking facility configured to fabricate one or more semiconductor masks based on the layout diagram.” Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 6-19 are rejected under 35 U.S.C. 103 as being unpatentable over HSEI et al (US 2016/0093603) in view of Haigh (US 9595536), and in further view of Zang et al (US 2019/0319112).
Regarding Claim 1, HSEI et al discloses a method (method [0018]) of manufacturing a semiconductor device (switching circuit 700 Fig 7-8) for which a corresponding layout diagram (layout design 800 [0079] Fig 8) is stored on a non-transitory computer-readable medium (non-transitory computer readable storage medium 614 [0067] Fig 6), the layout diagram (800) including:
active area patterns (layout patterns 852-856 [0079] Fig 8) extending in a first direction (horizontal x direction),
gate patterns (layout patterns 823-826 [0079] Fig 8) extending in a second direction (vertical y direction) perpendicular to the first direction (horizontal x direction) and overlying corresponding ones of the active area patterns (852-856), and
via-to-gate (VG) patterns (via layout patterns 872, 874, 876, 878, 879, 882, 884, and 886 [0083] Fig 8) overlying corresponding ones of the gate patterns (823-826), the method (method [0018]) comprising generating the layout diagram (800) including:
regarding first (852 and 856) and second ones (853 and 855) of the active area patterns (852-856) which
(1) are correspondingly nearest to a boundary (shown in annotated Fig 8) between, and
(2) are correspondingly in, first and second abutting cells (shown in annotated Fig 8), and
for each of the gate patterns (823-826) that intersects the first (852 and 856) or second active area pattern (853 and 855).
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HSEI et al does not disclose
selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value relative to the second direction; and
for each of the selected gate patterns, relative to a first size, setting a size of a corresponding cut-gate section to a second size;
the first size otherwise resulting in an overhang of a remnant portion of the gate pattern extending towards the boundary by a first length; and
the second size resulting in the overhang extending towards the boundary by a second length smaller than the first length.
Haigh, in the related art of semiconductor devices that include NAND devices, discloses
selecting ones among the gate patterns (shown in annotated Fig 87D viewed from 90 degrees) for which a first distance (shown in annotated Fig 87D viewed from 90 degrees) from a nearest corresponding VG pattern (shown in annotated Fig 87D viewed from 90 degrees) to a corresponding cut-gate section (first exposure cut mask M0 cut 1 [column 12, lines 1-19] Fig 87B viewed from 90 degrees or second exposure cut mask M0 cut 2 [column 12, lines 1-19] Fig 87 C viewed from 90 degrees) is equal to or greater than a first reference value relative (shown in annotated Fig 87D viewed from 90 degrees) to the second direction (vertical y direction).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify HSEI et al to include selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value relative to the second direction as taught by Haigh in order to manufacture gate electrodes of different sizes relative to the location of the vias and avoid spacing vias so close to each other that they increase the risk of manufacturing failure or spacing vias and cuts so close to each other that they increase the risk of manufacturing failure [column 2, lines 1-9]. Further, a person of ordinary skill in the art would have recognized that selecting among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section would be advantageous in that it would optimize the gate electrode density in the device such that there is improved electrical functioning while minimizing the risk of undesirable electrical effects that may damage or hinder the performance of the device (see MPEP 2143.I(D)).
The combination of HSEI et al and Haigh now discloses
selecting ones among the gate patterns (823-826 HSEI et al) for which a first distance (shown in annotated Fig 8 HSEI et al) from a nearest corresponding VG pattern (via layout patterns 872, 874, 876, 878, 879, 882, 884, and 886 [0083] Fig 8 HSEI et al) to a corresponding cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees Haigh/M0 cut 2 Fig 87 C viewed from 90 degrees Haigh) is equal to or greater than a first reference value relative (shown in annotate Fig 8 HSEI et al) to the second direction (horizontal x direction).
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for each of the selected gate patterns, relative to a first size, setting a size of a corresponding cut-gate section to a second size;
the first size otherwise resulting in an overhang of a remnant portion of the gate pattern extending towards the boundary by a first length; and
the second size resulting in the overhang extending towards the boundary by a second length smaller than the first length.
Zang et al, in the related art of semiconductor devices that include FET devices, discloses
for each of the selected gate patterns (gate formations 255 [0028] Fig 1), the size of the gate cut regions may be determined by the integrated circuit design unit (1540 [0061]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include changing the size of the gate cut regions in the vertical direction as taught by Zang et al in order to incorporate offsetting the gate electrodes in the vertical direction to help avoid spacing vias so close to each other that they increase the risk of manufacturing failure or spacing vias and cuts so close to each other that they increase the risk of manufacturing failure as referred to by Haigh [column 2, lines 1-9] and because it would have been an obvious matter of design choice to optimize the size of the cut-gate/gate electrode portion since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that changing the size of the gate cut regions in the vertical direction would be advantageous in allowing for gate electrode density to be optimized while avoiding them from being too close to each other to avoid manufacturing failure (see MPEP 2143.I(D)).
The combination of HSEI et al, Haigh, and Zang et al now discloses
for each of the selected gate patterns (gate formations 255 [0028] Fig 1 Zang et al/ layout patterns 823-826 [0079] Fig 8 HSEI et al/shown in annotated Fig 87D viewed from 90 degrees Haigh), relative to a first size (shown in annotated Fig 8 HSEI et al), setting a size (change in size [0061] Zang et al) of a corresponding cut-gate section (shown in annotated Fig 8 HSEI et al) to a second size (shown in annotated Fig 8 HSEI et al);
the first size (shown in annotated Fig 8 HSEI et al) otherwise resulting in an overhang (shown in annotated Fig 8 HSEI et al) of a remnant portion of the gate pattern (gate formations 255 [0028] Fig 1 Zang et al/ layout patterns 823-826 [0079] Fig 8 HSEI et al) extending towards the boundary by a first length (shown in annotated Fig 8 HSEI et al); and
the second size (shown in annotated Fig 8 HSEI et al) resulting in the overhang (shown in annotated Fig 8 HSEI et al) extending towards the boundary (shown above in annotated Fig 8 HSEI et al) by a second length (shown in annotated Fig 8 HSEI et al) smaller than the first length (shown in annotated Fig 8 HSEI et al).
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Regarding Claim 2, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 1 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: the second length (shown above in annotated Fig 8 HSEI et al) is a minimal permissible amount of overhang (shown above in annotated Fig 8 HSEI et al) of the remnant portion.
Regarding Claim 4, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 1 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: relative to the second direction (horizontal x direction, Fig 8 HSEI et al):
the first size (shown in annotated Fig 8 HSEI et al) results in a first gap (shown in annotated Fig 8 HSEI et al) between the cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees (Haigh) or M0 cut 2 Fig 87 C viewed from 90 degrees (Haigh)/shown in annotated Fig 8 HSEI et al) and the corresponding one of the first (852 and 856 Fig 8 HSEI et al) and second active area patterns (853 and 855 HSEI et al);
the second size (shown in annotated Fig 8 HSEI et al) results in a second gap (shown in annotated Fig 8 HSEI et al) between the cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees (Haigh) or M0 cut 2 Fig 87 C viewed from 90 degrees (Haigh)/shown in annotated Fig 8 HSEI et al) and the corresponding one of the first (852 and 856 Fig 8 HSEI et al) and second active area patterns (853 and 855 HSEI et al); and
a size of the second gap (shown in annotated Fig 8 HSEI et al) is about 6/9 of a size of the first gap (shown in annotated Fig 8 HSEI et al).
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The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
a size of the second gap is about 5/9 of a size of the first gap.
However, a person of ordinary skill in the art would know that the size of the gap is a result effective variable in that the smaller the second gap in comparison to the first gap, the greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a size of the second gap is about 5/9 of a size of the first gap as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the second gap relative to the first gap since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 6, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 1 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: relative to the second direction (horizontal x direction), a height of each cell is CH (shown in annotated Fig 8 HSEI et al); and as measured from the boundary, the second size is about 0.1*CH.
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The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein: relative to the second direction, a height of each cell is CH; and as measured from the boundary, the second size is about 0.05*CH.
However, a person of ordinary skill in the art would know that the size of the second size relative to the cell height CH is a result effective variable in that the smaller the second size, the greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a the second size is about 0.05 CH as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the second size relative to the cell height CH since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 7, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 6 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: as measured from the boundary (shown in annotated Fig 8 HSEI et al), the first size (shown above in annotated Fig 8 HSEI et al) is about 0.15*CH.
The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein: as measured from the boundary, the first size is about 0.1*CH.
However, a person of ordinary skill in the art would know that the size of the first size relative to the cell height CH is a result effective variable in that the smaller the first size, the greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a the first size is about 0.1 CH as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the first size relative to the cell height CH since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 8, HSEI et al discloses a method (method [0018]) of manufacturing a semiconductor device (switching circuit 700 Fig 7-8) for which a corresponding layout diagram (layout design 800 [0079] Fig 8) is stored on a non-transitory computer-readable medium (non-transitory computer readable storage medium 614 [0067] Fig 6),
the layout diagram (800) including active area patterns (layout patterns 852-856 [0079] Fig 8) extending in a first direction (horizontal x direction),
gate patterns (layout patterns 823-826 [0079] Fig 8) extending in a second direction (vertical y direction) perpendicular to the first direction (horizontal x direction) and overlying corresponding ones of the active area patterns (852-856), and
via-to-gate (VG) patterns (via layout patterns 872, 874, 876, 878, 879, 882, 884, and 886 [0083] Fig 8) overlying corresponding ones of the gate patterns (823-826),
the method (method [0018]) comprising generating the layout diagram (800) including:
regarding first (852 and 856) and second ones (853 and 855) of the active area patterns (852-856) which
(1) are correspondingly nearest to a boundary (shown in annotated Fig 8) between, and
(2) are correspondingly in, first and second abutting cells (shown in annotated Fig 8), and
for each of the gate patterns (823-826) that intersects the first (852 and 856) or second active area pattern (853 and 855).
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relative to a first size,
setting a size of a corresponding cut-gate section to a second size;
the first size otherwise resulting in an overhang of a remnant portion of the gate pattern extending towards the boundary by a first length; and
the second size resulting in the overhang extending towards the boundary by a second length smaller than the first length; and
selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to the corresponding cut-gate section is than a first reference value less than a first reference value relative to the second direction; and
for each of the selected gate patterns, reducing the size of the corresponding cut-gate section from the second size to the first size.
Haigh, in the related art of semiconductor devices that include NAND devices, discloses
selecting ones among the gate patterns (shown in annotated Fig 87D viewed from 90 degrees) for which a first distance (shown in annotated Fig 87D viewed from 90 degrees) from a nearest corresponding VG pattern (shown in annotated Fig 87D viewed from 90 degrees) to a corresponding cut-gate section (first exposure cut mask M0 cut 1 [column 12, lines 1-19] Fig 87B viewed from 90 degrees or second exposure cut mask M0 cut 2 [column 12, lines 1-19] Fig 87 C viewed from 90 degrees) is equal to or greater than a first reference value relative (shown in annotated Fig 87D viewed from 90 degrees) to the second direction (vertical y direction).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify HSEI et al to include selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value relative to the second direction as taught by Haigh in order to manufacture gate electrodes of different sizes relative to the location of the vias and avoid spacing vias so close to each other that they increase the risk of manufacturing failure or spacing vias and cuts so close to each other that they increase the risk of manufacturing failure [column 2, lines 1-9]. Further, a person of ordinary skill in the art would have recognized that selecting among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section would be advantageous in that it would optimize the gate electrode density in the device such that there is improved electrical functioning while minimizing the risk of undesirable electrical effects that may damage or hinder the performance of the device (see MPEP 2143.I(D)).
The combination of HSEI et al and Haigh now discloses
selecting ones among the gate patterns (823-826 HSEI et al) for which a first distance (shown in annotated Fig 8 HSEI et al) from a nearest corresponding VG pattern (via layout patterns 872, 874, 876, 878, 879, 882, 884, and 886 [0083] Fig 8 HSEI et al) to a corresponding cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees Haigh/M0 cut 2 Fig 87 C viewed from 90 degrees Haigh) is equal to or greater than a first reference value relative (shown in annotate Fig 8 HSEI et al) to the second direction (horizontal x direction).
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The combination of HSEI et al and Haigh does not disclose
relative to a first size, setting a size of a corresponding cut-gate section to a second size;
the first size otherwise resulting in an overhang of a remnant portion of the gate pattern extending towards the boundary by a first length; and
the second size resulting in the overhang extending towards the boundary by a second length smaller than the first length; and
for each of the selected gate patterns, reducing the size of the corresponding cut-gate section from the second size to the first size.
Zang et al, in the related art of semiconductor devices that include FET devices, discloses
for each of the selected gate patterns (gate formations 255 [0028] Fig 1), the size of the gate cut regions may be determined by the integrated circuit design unit (1540 [0061]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include changing the size of the gate cut regions in the vertical direction as taught by Zang et al in order to incorporate offsetting the gate electrodes in the vertical direction to help avoid spacing vias so close to each other that they increase the risk of manufacturing failure or spacing vias and cuts so close to each other that they increase the risk of manufacturing failure as referred to by Haigh [column 2, lines 1-9] and because it would have been an obvious matter of design choice to optimize the size of the cut-gate/gate electrode portion since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that changing the size of the gate cut regions in the vertical direction would be advantageous in allowing for gate electrode density to be optimized while avoiding them from being too close to each other to avoid manufacturing failure (see MPEP 2143.I(D)).
The combination of HSEI et al, Haigh, and Zang et al now discloses
for each of the selected gate patterns (gate formations 255 [0028] Fig 1 Zang et al/ layout patterns 823-826 [0079] Fig 8 HSEI et al/shown in annotated Fig 87D viewed from 90 degrees Haigh), relative to a first size (shown in annotated Fig 8 HSEI et al), setting a size (change in size [0061] Zang et al) of a corresponding cut-gate section (shown in annotated Fig 8 HSEI et al) to a second size (shown in annotated Fig 8 HSEI et al);
the first size (shown in annotated Fig 8 HSEI et al) otherwise resulting in an overhang (shown in annotated Fig 8 HSEI et al) of a remnant portion of the gate pattern (gate formations 255 [0028] Fig 1 Zang et al/ layout patterns 823-826 [0079] Fig 8 HSEI et al) extending towards the boundary by a first length (shown in annotated Fig 8 HSEI et al); and
the second size (shown in annotated Fig 8 HSEI et al) resulting in the overhang (shown in annotated Fig 8 HSEI et al) extending towards the boundary (shown above in annotated Fig 8 HSEI et al) by a second length (shown in annotated Fig 8 HSEI et al) smaller than the first length (shown in annotated Fig 8 HSEI et al).
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for each of the selected gate patterns (823-826 Fig 8 HSEI et al), reducing the size of the corresponding cut-gate section (shown in annotated Fig 8 HSEI et al) from the second size (shown in annotated Fig 8 HSEI et al) to the first size (shown in annotated Fig 8 HSEI et al).
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Regarding Claim 9, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 8 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: the second length (shown above in annotated Fig 8 HSEI et al) is a minimal permissible amount of overhang (shown above in annotated Fig 8 HSEI et al) of the remnant portion.
Regarding Claim 10, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 8 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: each cut-gate section (M0 cut 1 shown above in Fig 87B viewed from 90 degrees Haigh/M0 cut 2 shown above in Fig 87 C viewed from 90 degrees Haigh) includes an initial cutting-area pattern (shown in annotated Fig 8 HSEI et al); and
the setting includes: adding a supplemental cutting-area pattern (shown in annotated Fig 8 HSEI et al) to abut the initial cutting-area pattern (shown in annotated Fig 8 HSEI et al) which thereby increases the size of the corresponding cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees Haigh/M0 cut 2 Fig 87 C viewed from 90 degrees Haigh) to the second value (shown in annotated Fig 8 HSEI et al)).
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Regarding Claim 11, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 10 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: the reducing includes: removing the supplemental cutting-area pattern (shown above in annotated Fig 8 HSEI et al) to abut the initial cutting- area pattern (shown above in annotated Fig 8 HSEI et al) which thereby increases the size of the corresponding cut-gate section (M0 cut1/M0 cut 2 corresponding to the second size) to the second value (shown above in annotated Fig 8 HSEI et al).
Regarding Claim 12, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 8 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: relative to the second direction (horizontal x direction, Fig 8 HSEI et al):
the first size (shown in annotated Fig 8 HSEI et al) results in a first gap (shown in annotated Fig 8 HSEI et al) between the cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees (Haigh) or M0 cut 2 Fig 87 C viewed from 90 degrees (Haigh)/shown in annotated Fig 8 HSEI et al) and the corresponding one of the first (852 and 856 Fig 8 HSEI et al) and second active area patterns (853 and 855 HSEI et al);
the second size (shown in annotated Fig 8 HSEI et al) results in a second gap (shown in annotated Fig 8 HSEI et al) between the cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees (Haigh) or M0 cut 2 Fig 87 C viewed from 90 degrees (Haigh)/shown in annotated Fig 8 HSEI et al) and the corresponding one of the first (852 and 856 Fig 8 HSEI et al) and second active area patterns (853 and 855 HSEI et al); and
a size of the second gap (shown in annotated Fig 8 HSEI et al) is about 6/9 of a size of the first gap (shown in annotated Fig 8 HSEI et al).
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The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
a size of the second gap is about 5/9 of a size of the first gap.
However, a person of ordinary skill in the art would know that the size of the gap is a result effective variable in that the smaller the second gap in comparison to the first gap, the greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a size of the second gap is about 5/9 of a size of the first gap as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the second gap relative to the first gap since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 13, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 8 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: relative to the second direction (horizontal x direction), a height of each cell is CH (shown in annotated Fig 8); and as measured from the boundary, the second size is about 0.1*CH.
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The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein: relative to the second direction, a height of each cell is CH; and as measured from the boundary, the second size is about 0.05*CH.
However, a person of ordinary skill in the art would know that the size of the second size relative to the cell height CH is a result effective variable in that the smaller the second size, the greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a the second size is about 0.05 CH as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the second size relative to the cell height CH since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 14, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 13 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: as measured from the boundary (shown in annotated Fig 8), the first size (shown above in annotated Fig 8) is about 0.15*CH.
The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein: as measured from the boundary, the first size is about 0.1*CH.
However, a person of ordinary skill in the art would know that the size of the first size relative to the cell height CH is a result effective variable in that the smaller the first size, the greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a the first size is about 0.1 CH as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the first size relative to the cell height CH since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 15, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 8 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: relative to the second direction (horizontal x direction): the first size (shown in annotated Fig 8 HSEI et al) results in a first gap (shown in annotated Fig 8 HSEI et al) between the cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees (Haigh) or M0 cut 2 Fig 87 C viewed from 90 degrees (Haigh)/shown in annotated Fig 8 HSEI et al) and the corresponding one of the first (852 and 856 Fig 8 HSEI et al) and second active area patterns (853 and 855 Fig 8 HSEI et al);
relative to the second direction (horizontal x direction), a height of each cell is CH (shown in annotated Fig 8 HSEI et al); and
the first gap (shown in annotated Fig 8 HSEI et al) is about 0.1*CH.
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The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein, the first gap is about 0.01*CH.
However, a person of ordinary skill in the art would know that the size of the first gap relative to the cell height CH is a result effective variable in that the smaller the first gap, the greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a the first gap is about 0.01 CH as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the first gap relative to the cell height CH since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 16, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 8 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: relative to the second direction (horizontal x direction): the second size (shown in annotated Fig 8 HSEI et al) results in a second gap (shown in annotated Fig 8 HSEI et al) between the cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees (Haigh) or M0 cut 2 Fig 87 C viewed from 90 degrees (Haigh)/shown in annotated Fig 8 HSEI et al) and the corresponding one of the first (852 and 856 Fig 8 HSEI et al) and second active area patterns (853 and 855 Fig 8 HSEI et al);
relative to the second direction (horizontal x direction), a height of each cell is CH (shown in annotated Fig 8 HSEI et al); and
the second gap (shown in annotated Fig 8 HSEI et al) is about 0.05*CH.
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The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein, the second gap is about 0.25*CH.
However, a person of ordinary skill in the art would know that the size of the first gap relative to the cell height CH is a result effective variable in that the larger the second gap relative to the first gap, the closer the electrodes can be to each other which would result in a greater the quantity of electrode material in the device which would improve the electrical function of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein a the second gap is about 0.25 CH as taught by HSEI et al in order to optimize the quantity of electrode material in the device which would improve the electrical function of the device and because it would have been an obvious matter of design choice to optimize the size of the second gap relative to the cell height CH since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A), and further because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 17, HSEI et discloses
a method (method [0018]) of manufacturing a semiconductor device (switching circuit 700 Fig 7-8) for which a corresponding layout diagram (layout design 800 [0079] Fig 8) is stored on a non-transitory computer-readable medium (non-transitory computer readable storage medium 614 [0067] Fig 6),
the layout diagram (800) including active area patterns (layout patterns 852-856 [0079] Fig 8) extending in a first direction (horizontal x direction),
gate patterns (layout patterns 823-826 [0079] Fig 8) extending in a second direction (vertical y direction) perpendicular to the first direction (horizontal x direction) and overlying corresponding ones of the active area patterns (852-856), and
via-to-gate (VG) patterns (via layout patterns 872, 874, 876, 878, 879, 882, 884, and 886 [0083] Fig 8) overlying corresponding ones of the gate patterns (823-826),
the method (method [0018]) comprising generating the layout diagram (800) including:
regarding first (852 and 856) and second ones (853 and 855) of the active area patterns (852-856) which
(1) are correspondingly nearest to a boundary (shown in annotated Fig 8) between, and
(2) are correspondingly in, first and second abutting cells (shown in annotated Fig 8), and
for each of the gate patterns (823-826) that intersects the first (852 and 856) or second active area pattern (853 and 855).
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HSEI et al does not disclose
selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value relative to the second direction; and
the selected gate patterns representing a majority of the intersecting gate patterns;
for each of the selected gate patterns, relative to a first size, setting a size of a corresponding cut-gate section to a second size;
the first size otherwise resulting in an overhang of a remnant portion of the gate pattern extending towards the boundary by a first length; and
the second size resulting in the overhang extending towards the boundary by a second length smaller than the first length.
Haigh, in the related art of semiconductor devices that include NAND devices, discloses
selecting ones among the gate patterns (shown in annotated Fig 87D viewed from 90 degrees) for which a first distance (shown in annotated Fig 87D viewed from 90 degrees) from a nearest corresponding VG pattern (shown in annotated Fig 87D viewed from 90 degrees) to a corresponding cut-gate section (first exposure cut mask M0 cut 1 [column 12, lines 1-19] Fig 87B viewed from 90 degrees or second exposure cut mask M0 cut 2 [column 12, lines 1-19] Fig 87 C viewed from 90 degrees) is equal to or greater than a first reference value relative (shown in annotated Fig 87D viewed from 90 degrees) to the second direction (vertical y direction).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify HSEI et al to include selecting ones among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value relative to the second direction as taught by Haigh in order to manufacture gate electrodes of different sizes relative to the location of the vias and avoid spacing vias so close to each other that they increase the risk of manufacturing failure or spacing vias and cuts so close to each other that they increase the risk of manufacturing failure [column 2, lines 1-9]. Further, a person of ordinary skill in the art would have recognized that selecting among the gate patterns for which a first distance from a nearest corresponding VG pattern to a corresponding cut-gate section would be advantageous in that it would optimize the gate electrode density in the device such that there is improved electrical functioning while minimizing the risk of undesirable electrical effects that may damage or hinder the performance of the device (see MPEP 2143.I(D)).
The combination of HSEI et al and Haigh now discloses
selecting ones among the gate patterns (823-826 HSEI et al) for which a first distance (shown in annotated Fig 8 HSEI et al) from a nearest corresponding VG pattern (via layout patterns 872, 874, 876, 878, 879, 882, 884, and 886 [0083] Fig 8 HSEI et al) to a corresponding cut-gate section (M0 cut 1 Fig 87B viewed from 90 degrees Haigh/M0 cut 2 Fig 87 C viewed from 90 degrees Haigh) is equal to or greater than a first reference value relative (shown in annotate Fig 8 HSEI et al) to the second direction (horizontal x direction),
the selected gate patterns (823-826 Fig 8 HSEI et al) representing a majority (4/6 intersecting gate patterns would be approximately 66.7 percent) of the intersecting gate patterns (822-826 and 828 Fig 8 HSEI et al);
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for each of the selected gate patterns, relative to a first size, setting a size of a corresponding cut-gate section to a second size;
the first size otherwise resulting in an overhang of a remnant portion of the gate pattern extending towards the boundary by a first length; and
the second size resulting in the overhang extending towards the boundary by a second length smaller than the first length.
Zang et al, in the related art of semiconductor devices that include FET devices, discloses
for each of the selected gate patterns (gate formations 255 [0028] Fig 1), the size of the gate cut regions may be determined by the integrated circuit design unit (1540 [0061]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include changing the size of the gate cut regions in the vertical direction as taught by Zang et al in order to incorporate offsetting the gate electrodes in the vertical direction to help avoid spacing vias so close to each other that they increase the risk of manufacturing failure or spacing vias and cuts so close to each other that they increase the risk of manufacturing failure as referred to by Haigh [column 2, lines 1-9] and because it would have been an obvious matter of design choice to optimize the size of the cut-gate/gate electrode portion since such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that changing the size of the gate cut regions in the vertical direction would be advantageous in allowing for gate electrode density to be optimized while avoiding them from being too close to each other to avoid manufacturing failure (see MPEP 2143.I(D)).
The combination of HSEI et al, Haigh, and Zang et al now discloses
for each of the selected gate patterns (gate formations 255 [0028] Fig 1 Zang et al/ layout patterns 823-826 [0079] Fig 8 HSEI et al/shown in annotated Fig 87D viewed from 90 degrees Haigh), relative to a first size (shown in annotated Fig 8 HSEI et al), setting a size (change in size [0061] Zang et al) of a corresponding cut-gate section (shown in annotated Fig 8 HSEI et al) to a second size (shown in annotated Fig 8 HSEI et al);
the first size (shown in annotated Fig 8 HSEI et al) otherwise resulting in an overhang (shown in annotated Fig 8 HSEI et al) of a remnant portion of the gate pattern (gate formations 255 [0028] Fig 1 Zang et al/ layout patterns 823-826 [0079] Fig 8 HSEI et al) extending towards the boundary by a first length (shown in annotated Fig 8 HSEI et al); and
the second size (shown in annotated Fig 8 HSEI et al) resulting in the overhang (shown in annotated Fig 8 HSEI et al) extending towards the boundary (shown above in annotated Fig 8 HSEI et al) by a second length (shown in annotated Fig 8 HSEI et al) smaller than the first length (shown in annotated Fig 8 HSEI et al).
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a system of manufacturing a semiconductor device for which a corresponding layout diagram is stored on a non-transitory computer-readable medium,
the system comprising at least one processor and at least one memory including computer program code for one or more programs,
wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute a method of generating the layout diagram.
HSEI et al, in the related art of semiconductor devices that include methods of processing cutting layouts, discloses
a system (IC designing system 600 [0066] Fig 6) of manufacturing a semiconductor device (device in embodiments of Fig 1A-5 [0067]) for which a corresponding layout diagram (layout diagrams for embodiments of Fig 1A-5) is stored on a non-transitory computer-readable medium (non-transitory readable storage medium 614 [0067] Fig 6),
the system (600 Fig 6) comprising at least one processor (hardware processor 612 [0067] Fig 6) and at least one memory (614 Fig 6) including computer program code (encoded with i.e., storing, a set of instruction 614a, a circuit schematic 614b, a circuit layout 614c, a modified layout 614d, or any intermediate data 614e for executing the set of instructions 614a [0067] Fig 6) for one or more programs (614a-d Fig 6),
wherein the at least one memory (614 Fig 6), the computer program code (encoded) and the at least one processor (612 Fig 6) are configured to cause the system (600 Fig 6) to execute a method of generating the layout diagram (the designing system 600 includes functionalities such as checking CUT layout patterns, merging CUT layout patterns, or generating remedial connecting layout patterns consistent with embodiments of Figs 1A-5 [0067] Fig 6, which then include layout diagrams of Fig 1A-5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al, as applied to claim 17, to include a system of manufacturing a semiconductor device as taught by HSEI et al in order to generate the layout diagram and execute the manufacturing process of the device. Further, a person of ordinary skill in the art would have recognized that having a system of manufacturing a semiconductor device would allow for a fabrication process that allows for finer spatial resolution [0022] that is cost effective and efficient [0001] (see MPEP 2143.I(D)).
Regarding Claim 18, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 17 as explained above. The combination of HSEI et al, Haigh, and Zang et al further discloses
wherein: the selected gate patterns (823-826 Fig 8 HSEI et al) represent at least about 66% (4/6 intersecting gate patterns would be approximately 66.7 percent) of the intersecting gate patterns (822, 823, 824, 825, 826, 828 Fig 8 HSEI et al).
The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein: the selected gate patterns represent at least about 75% of the intersecting gate patterns.
However, a person of ordinary skill in the art would know that the amount of gate electrodes selected would be a result effective variable in that having more selected gate electrodes would allow for more electrical function in a smaller amount of space which would optimize the electrical functioning capability of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein: the selected gate patterns represent at least about 75% of the intersecting gate patterns as taught by HSEI et al in order to have more electrical function in a smaller amount of space and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that having more electrical function in a smaller amount of space would optimize the electrical functional capability of the device while minimizing the risk of damage from undesirable electrical effects e.g. shorting (see MPEP 2143.I(D)).
Regarding Claim 19, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 18 as explained above. The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein: the selected gate patterns represent at least about 87.5% of the intersecting gate patterns.
However, a person of ordinary skill in the art would know that the amount of gate electrodes selected would be a result effective variable in that having more selected gate electrodes would allow for more electrical function in a smaller amount of space which would optimize the electrical functioning capability of the device.
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include wherein: the selected gate patterns represent at least about 87.5% of the intersecting gate patterns as taught by HSEI et al in order to have more electrical function in a smaller amount of space and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that having more electrical function in a smaller amount of space would optimize the electrical functional capability of the device while minimizing the risk of damage from undesirable electrical effects e.g. shorting (see MPEP 2143.I(D)).
Claims 3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over HSEI et al (US 2016/0093603) in view of Haigh (US 9595536), and Zang et al (US 2019/0319112), and in further view of Liu et al (US 2018/0336293).
Regarding Claim 3, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 1 as explained above. The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
further comprising: based on the layout diagram, at least one of:
(A) making one or more photolithographic exposure;
(B) fabricating one or more semiconductor masks; or
(C) fabricating at least one component in a layer of a semiconductor integrated circuit.
Liu et al, in the related art of semiconductor devices that include layout diagrams, discloses
further comprising at least one of: a first masking facility (masking facility [0174]-[0175]) configured to fabricate one or more semiconductor masks (masks [0174]-[0175]) based on based on the layout diagram (layout diagram [0174]-[0175]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include a first masking facility configured to fabricate one or more semiconductor masks based on the layout diagram as taught by Liu et al in order to in order to protect areas of the device during the cutting procedure [0165]. Further, a person of ordinary skill in the art would have recognized that having one or more semiconductor masks would be advantageous in allowing for protection of the underlying areas of the device during the lithographic process [0165] (see MPEP 2143.I(D)).
Regarding Claim 20, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 17 as explained above. The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
further comprising at least one of: a first masking facility configured to fabricate one or more semiconductor masks based on the layout diagram; or
a second masking facility configured to perform one or more lithographic exposures based on the layout diagram; or
a fabricating facility configured to fabricate at least one component in a layer of a semiconductor device based on the layout diagram.
Liu et al, in the related art of semiconductor devices that include layout diagrams, discloses
further comprising at least one of: a first masking facility (masking facility [0174]-[0175]) configured to fabricate one or more semiconductor masks (masks [0174]-[0175]) based on based on the layout diagram (layout diagram [0174]-[0175]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include a first masking facility configured to fabricate one or more semiconductor masks based on the layout diagram as taught by Liu et al in order to in order to protect areas of the device during the cutting procedure [0165]. Further, a person of ordinary skill in the art would have recognized that having one or more semiconductor masks would be advantageous in allowing for protection of the underlying areas of the device during the lithographic process [0165] (see MPEP 2143.I(D)).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over HSEI et al (US 2016/0093603) in view of Haigh (US 9595536), and Zang et al (US 2019/0319112), and in further view of Kronholz et al (US 8609498).
Regarding Claim 5, the combination of HSEI et al, Haigh, and Zang et al discloses the limitations of claim 4 as explained above. The combination of HSEI et al, Haigh, and Zang et al does not directly disclose
wherein: the size of the second gap is about 5 nanometers (nm) and the size of the first gap is about 9 nm.
Kronholz et al, in the related art of semiconductors that include transistors, discloses
a transistor wherein the length of a gate electrode structure is 30 nm or less [column 8, lines 30-40].
Absent any disclosed criticality to the claimed range, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of HSEI et al, Haigh, and Zang et al to include optimizing the gate electrode to be 30 nm or less as taught by Kronholz et al and further optimize the size of the first gap and the second gap in order to advantageously minimize the size to meet the critical dimensions [column 8, lines 30-40], and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. BISWAS et al (US 2019/0065659) which discloses a system for generating a layout diagram of a semiconductor device including at least one processor and at least one memory including computer code for one or more programs [0097], and Yang et al (US 2018/0082846) which discloses a fabrication method for a FinFET device [0027].
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812