Prosecution Insights
Last updated: July 17, 2026
Application No. 18/448,193

COMPOSITE SUBSTRATES AND SEMICONDUCTOR DEVICE STRUCTURES

Non-Final OA §102§103§112
Filed
Aug 11, 2023
Priority
Aug 12, 2022 — CN 202222129523.9
Examiner
MIYOSHI, JESSE Y
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Enkris Semiconductor Inc.
OA Round
1 (Non-Final)
57%
Grant Probability
Moderate
1-2
OA Rounds
8m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
276 granted / 484 resolved
-11.0% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
30 currently pending
Career history
541
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
75.6%
+35.6% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 484 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of device embodiment 3 as shown in fig. 10 (claims 1-6, 8-16 readable thereon, claim 7 withdrawn) in the reply filed on 3/10/2026 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6, 8-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the side of the DBR layer” at line 4. It is unclear as to whether the limitation is referring to “a side of the base” or to another element. Claim 14 recites the limitation “the side of the DBR layer” at line 6. It is unclear as to whether the limitation is referring to “a side of the base” or to another element. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 9, 10, and 14-16 is/are rejected under 35 U.S.C. 102(a)(1), as best understood, as being anticipated by Chiu et al. (US PGPub 2014/0131727; hereinafter “Chiu”). Re claim 1: Chiu teaches (e.g. fig 6) a composite substrate, comprising: a base (110, 111); a distributed Bragg reflector (DBR) layer (DBR 130; e.g. paragraph 17) on a side (upper side of 110,111; hereinafter “S”) of the base (110, 111); and a growing substrate (upper surface portion of i-GaN 70; e.g. paragraph 19; hereinafter “GS”) on the side (upper side of DBR 130) of the DBR layer (130) away from the base (110, 111). Re claim 2: Chiu teaches the composite substrate according to claim 1, further comprising: a protecting layer (lower portions of i-GaN 70 that are between portions of 111; e.g. paragraph 19; hereinafter “PL”), wherein the protecting layer (PL) covers a top surface (top surface of 130) of the DBR layer (130). Re claim 3: Chiu teaches the composite substrate according to claim 2, wherein a light transmittance of light (light emitted from active layer 150) of at least one wavelength passing through the protecting layer (PL) and the growing substrate (GS) exceeds 70% (claimed properties are presumed to be present when the prior art structure is substantially identical to the claimed structure, see MPEP 2112.01{i)). Re claim 4: Chiu teaches the composite substrate according to claim 1, wherein the base (110, 111) comprises a patterned base (110 is provided with protrusions 111), and the top surface of the base (110, 111) is provided with a trench (regions between 111; hereinafter “T”), and the DBR layer (130) is in the trench (T). Re claim 5: Chiu teaches the composite substrate according to claim 4, wherein a top surface of the DBR layer (130) is lower than the top surface of the base (110, 111). Re claim 6: Chiu teaches the composite substrate according to claim 4, further comprising: the protecting layer (lower portions of i-GaN 70 that are between portions of 111; e.g. paragraph 19; hereinafter “PL”) covers the DBR layer (130) and the base (110, 111), and the growing substrate (GS) is bonded to the protecting layer (PL). Re claim 9: Chiu teaches the composite substrate according to claim 1, wherein a material of the base (sapphire substrate 110, 111; e.g. paragraph 20) comprises at least one of Si, SiC, AIN, Al2O3, or diamond. Re claim 10: Chiu teaches the composite substrate according to claim 1, wherein the growing substrate (GS) comprises a monocrystalline-material layer (GaN layer 70; e.g. paragraph 21). Re claim 14: Chiu teaches (e.g. fig 6) a semiconductor device structure, comprising a composite substrate (110, 111, 120, 130, 70; hereinafter “CS) and an LED unit (140, 150, 160; hereinafter “LU”), wherein the composite substrate (CS) comprises: a base (110, 111); a DBR layer (130) on a side (upper side of 110, 111; hereinafter “S”) of the base (110, 111); and a growing substrate (upper surface portion of i-GaN 70; e.g. paragraph 19; hereinafter “GS”) on the side (S) of the DBR layer (130) away from the base (110, 111); and the LED unit (LU) comprises: a first semiconductor layer (140), on the growing substrate (GS); an active layer (150), on a surface of the first semiconductor layer (140); and a second semiconductor layer (160), on a surface of the active layer (150); wherein conductive types of the first semiconductor layer (140) and the second semiconductor layer (160) are opposite (n-type GaN layer 140 and the p-type GaN layer 160; e.g. paragraph 19). Re claim 15: Chiu teaches the semiconductor device structure according to claim 14, wherein the base (110, 111) is provided with DBR layers (130), and there are LED units (LU), each of the LED units (LU) corresponding to one of the DBR layers (130). Re claim 16: Chiu teaches the semiconductor device structure according to claim 14, wherein the composite substrate (CS) comprises DBR layers (130), and at least one of: cross-sectional areas of the DBR layers are different; or spaces between adjacent DBR layers (130) of the DBR layers (130) are different (sloped sidewalls provide for a plurality of different spacings between adjacent DBR layers). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu as applied to claim 1 above, and further in view of Jain et al. (US PGPub 2016/0118531; hereinafter “Jain”). Re claim 8: Chiu teaches the composite substrate according to claim 2, wherein a material of the protecting layer (PL) comprises GaN. Chiu is silent as to the material of the protecting layer comprises at least one of Si, Al2O3, or AIN. Jain teaches that substrate having a sapphire substrate can have a buffer/protecting layer made from AlN 14 (e.g. paragraph 34) that interfaces well with the GaN material of the LED structure. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the AlN protecting layer as taught by Jain in the device of Chiu in order to have the predictable result of using a known material which interfaces well with the GaN materials of the upper LED structure and reduce lattice structures so that the LED can have better light emitting performance. Re claim 11: Chiu teaches the composite substrate according to claim 10, wherein a material of the growing substrate (GS) comprises GaN. Chiu is silent as to the material of the growing substrate comprises at least one of Si, Al2O3, or AIN. Jain teaches that substrate having a sapphire substrate can have a buffer/growth substrate made from AlN 14 (e.g. paragraph 34) that interfaces well with the GaN material of the LED structure. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the AlN growth substrate as taught by Jain in the device of Chiu in order to have the predictable result of using a known material which interfaces well with the GaN materials of the upper LED structure and reduce lattice structures so that the LED can have better light emitting performance. Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu as applied to claim 1 above, and further in view of Huang et al. (US PGPub 2009/0114935; hereinafter “Huang”). Re claim 13: Chiu teaches a Bragg reflector but is silent as to explicitly teaching the composite substrate according to claim 1, wherein a material of the DBR layer comprises a SiN layer and a SiO2 layer that are periodically stacked, a SiO2 layer and an Al2O3 layer that are periodically stacked, an AIN layer and an Al2O3 layer that are periodically stacked, or a fluorine doped SiO2 layer and a SiO2 layer that are periodically stacked. Huang teaches a material of the DBR layer comprises a SiN layer and a SiO2 layer that are periodically stacked, a SiO2 layer and an Al2O3 layer (stack of high and low refractive index layers chosen from SiO2, SiN, AlN, and Al2O3; e.g. paragraph 38) that are periodically stacked, an AIN layer and an Al2O3 layer that are periodically stacked, or a fluorine doped SiO2 layer and a SiO2 layer that are periodically stacked. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the alternative material for a DBR as taught by Huang in the device of Chiu in order to have the predictable result of reducing costs by using a known material that is readily available for the production of a DBR. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Aug 11, 2023
Application Filed
Apr 14, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
57%
Grant Probability
76%
With Interview (+18.7%)
3y 7m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 484 resolved cases by this examiner. Grant probability derived from career allowance rate.

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