Prosecution Insights
Last updated: April 19, 2026
Application No. 18/448,287

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §102§103§112
Filed
Aug 11, 2023
Examiner
CHAN, CANDICE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
3y 3m
To Grant
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
399 granted / 547 resolved
+4.9% vs TC avg
Strong +19% interview lift
Without
With
+18.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
49 currently pending
Career history
596
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
49.6%
+9.6% vs TC avg
§102
28.8%
-11.2% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 547 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office action is in response to the election filed 21 January 2026. Claims 1-29 are currently pending; claims 20-29 have been withdrawn by Applicant. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1-19, in the reply filed on 21 January 2026 is acknowledged. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "244" and "242" have both been used to designate the “second dopant”; it is believed reference character “242” should point to the material surrounding the second dopant (second insulating material layer). Reference characters “222” and “224” have both been used to designate the “first dopant”; it is believed reference character “222” should point to the material surrounding the first dopant (first insulating material layer). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 10 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites the limitation "the dead region" in line 2. It is unclear which “dead region” this limitation is intended to refer to, i.e., the dead region of the first selector layer or the dead region of the second selector layer. For the purposes of examination, it is assumed the above limitation is intended to refer to one of: the dead region of the first selector layer or the dead region of the second selector layer. Claim 11 recites the limitation "the dead region" in line 1. It is unclear which “dead region” this limitation is intended to refer to, i.e., the dead region of the first selector layer or the dead region of the second selector layer. For the purposes of examination, it is assumed the above limitation is intended to refer to one of: the dead region of the first selector layer or the dead region of the second selector layer. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-9 and 11-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0183945 A1 to Song (hereinafter “Song”). Regarding independent claim 1, Song (Fig. 7E) discloses a semiconductor device comprising: first and second conductive layers 310 (¶ 0095; ¶ 0109 - “second electrode layer”) spaced apart from each other; and a memory cell interposed between the first and second conductive layers, wherein the memory cell includes: a first selector layer 320 (¶ 0097); a second selector layer 340 (¶ 0099) spaced apart from the first selector layer (Fig. 7E); and an insulating layer 330 (¶ 0106) interposed between the first selector layer and the second selector layer (Fig. 7E). Regarding claim 2, Song discloses the semiconductor device according to claim 1. The limitations “wherein the first selector layer is turned on at or above a first sub-threshold voltage, the second selector layer is turned on at or above a second sub-threshold voltage, and a soft breakdown of the insulating layer occurs at or above a breakdown voltage” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP § 2114(I). Regarding claim 3, Song (Fig. 7E) discloses the semiconductor device according to claim 1, wherein a thickness of the insulating layer 330 is smaller than a thickness of the first selector layer 320 and a thickness of the second selector layer 340 (Fig. 7E; ¶ 0106). Regarding claim 4, Song discloses the semiconductor device according to claim 1, wherein a thickness of the insulating layer 330 has a range of several to several tens of nm (¶ 0037). Regarding claim 5, Song (Fig. 7E) discloses the semiconductor device according to claim 1, wherein a thickness of the first selector layer 320 has a range of 90% to 110% of a thickness of the second selector layer 340 (Fig. 7E). Regarding claim 6, Song (Fig. 7E) discloses the semiconductor device according to claim 1, wherein the first selector layer 320 includes a first insulating material layer (¶ 0097) and a first dopant doped 325 (¶ 0098) in the first insulating material layer to create a shallow trap providing a passage for a conductive carrier to move (see ¶ 0030), and the second selector layer 340 includes a second insulating material layer (¶ 0099) and a second dopant 345 (¶ 0100) doped in the second insulating material layer to create a shallow trap providing a passage for a conductive carrier to move (see ¶¶ 0033, 30). Regarding claim 7, Song (Fig. 7E) discloses the semiconductor device according to claim 6, wherein the first insulating material layer, the second insulating material layer, and the insulating layer 330 include a same insulating material 322 (¶¶ 0097, 99, 0106). Regarding claim 8, Song (Fig. 7E) discloses the semiconductor device according to claim 1, wherein each of the first and second selector layers 320/340 includes a dead region corresponding to an edge from a sidewall of each of the first and second selector layers (“dead region” interpreted to include edge regions that do not contain dopants 325/345 in 320/340, respectively, as in Fig. 7E) and not functioning as a selector (this limitation is considered functional language), and an active region (center regions containing dopants 325/345 in 320/340, respectively, as in Fig. 7E) having a sidewall surrounded by the dead region (Fig. 7E) and functioning as a selector (this limitation is considered functional language). The limitations identified as functional language do not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 9, Song (Fig. 7E) discloses the semiconductor device according to claim 8, wherein the active region of the first selector layer 320 includes a first insulating material layer (¶ 0097) and a first dopant 325 (¶ 0098) having a first concentration doped into the first insulating material layer to create a shallow trap providing a passage for a conductive carrier to move (see ¶ 0030), the dead region of the first selector layer includes the first insulating material layer and the first dopant having a second concentration equal to or greater than 0 and lower than the first concentration (“dead region” interpreted to include edge regions that contain less dopant 325 in 320 as in Fig. 7E; thus the “second concentration” is greater than 0 and lower than the first concentration), the active region of the second selector layer 340 includes a second insulating material layer (¶ 0099) and a second dopant 345 (¶ 0100) having a third concentration doped into the second insulating material layer to create a shallow trap providing a passage for a conductive carrier to move, and the dead region of the second selector layer includes the second insulating material layer and the second dopant having a fourth concentration equal to or greater than 0 and lower than the third concentration (“dead region” interpreted to include edge regions that contain less dopant 345 in 340 as in Fig. 7E; thus the “fourth concentration” is greater than 0 and lower than the third concentration). Regarding claim 11, as best understood, Song (Fig. 7E) discloses the semiconductor device according to claim 8, wherein the dead region has a width that decreases from top to bottom (Fig. 7E - each dead region may be defined to have a width that decreases from top to bottom). Regarding claim 12, Song discloses the semiconductor device according to claim 2. The limitations “wherein a first threshold voltage is a sum of the first sub-threshold voltage, the second sub-threshold voltage, and the breakdown voltage, wherein a conductive path is formed in each of the first selector layer, the insulating layer, and the second selector layer during a write operation, wherein a write voltage applied during the write operation has a magnitude greater than the first threshold voltage” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 13, Song discloses the semiconductor device according to claim 12. The limitations “wherein a second threshold voltage is a sum of the first sub-threshold voltage and the second sub-threshold voltage, wherein, during an erase operation, a conductive path is formed in each of the first selector layer and the second selector layer, and a conductive path previously formed in the insulating layer disappears, wherein an erase voltage applied during the erase operation has a magnitude greater than the second threshold voltage and less than the first threshold voltage” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 14, Song discloses the semiconductor device according to claim 13. The limitations “wherein a polarity of the write voltage is the same as a polarity of the erase voltage” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 15, Song discloses the semiconductor device according to claim 13. The limitations “wherein a read voltage applied during a read operation for reading a resistance state of the memory cell has a magnitude greater than the second threshold voltage and less than the erase voltage“ are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 16, Song discloses the semiconductor device according to claim 15. The limitations “wherein a polarity of the read voltage is the same as a polarity of the write voltage and a polarity of the erase voltage” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 17, Song discloses the semiconductor device according to claim 13. The limitations “wherein the conductive path of the insulating layer disappears by Joule's heat generated according to the erase voltage” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 18, Song discloses the semiconductor device according to claim 13. The limitations “wherein at least part of the conductive path of the insulating layer disappears” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Regarding claim 19, Song discloses the semiconductor device according to claim 13, The limitations “wherein the conductive path of the insulating layer remains even after power is removed, until the erase voltage is applied” are considered functional language that does not structurally distinguish the claimed invention over the prior art. Song discloses the structure as recited in the claim as currently drafted, thus the structure of Song is presumed capable of the functionally defined limitations of the claimed device. MPEP 2114 (I). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Song as applied to claims 1, 8, and 9 above, and further in view of US 2011/0101298 A1 to Tang et al. (hereinafter “Tang”). Regarding claim 10, as best understood, Song (Fig. 7E) discloses the semiconductor device according to claim 9, wherein the first and second dopants include arsenic (¶ 0031), and the dead region includes arsenic (Fig. 7E, ¶ 0098, ¶ 0031). Song fails to expressly disclose the presence of a chlorine-based element in the dead region. In the same field of endeavor, Tang discloses a method of making memory devices including a reactive ion etching process using chlorine-based gas (¶ 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that etching processes are used to form semiconductor devices (see structure of Song, Fig. 6) and that the use of conventional etch processes such as that of Tang would result in the presence of chlorine-based elements (i.e., residue) on/in the etched surfaces, such as the dead region of Song and thus yielding the recited features. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CANDICE Y. CHAN Examiner Art Unit 2813 7 March 2026 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Aug 11, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+18.8%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 547 resolved cases by this examiner. Grant probability derived from career allow rate.

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