Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 08/11/23. Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement filed on 08/11/23 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. §102(a)(2) as being unpatentable over Maejima (US 20220301615 A1).
Regarding claim 1, Maejima discloses a semiconductor device comprising: a bit line sense amplifier (BLSA) circuit pattern on a substrate (see fig 19 disclosing SAM); a column circuit pattern on the substrate adjacent to the BLSA pattern (see WLSW, in fig 19); and a cell array including: bit lines on the BLSA circuit pattern and the column circuit pattern (see Bit line BL in fig 19 are included in cell array 10), each of the bit lines extending in a first direction and spaced apart from each other in a second direction crossing the first direction (see fig 17, disclosing parallel bit lines); gate electrodes spaced apart from each other in the first direction (see fig 12, disclosing gate conductors GC spaced apart from each other), each of the gate electrodes extending in the second direction on the bit lines (see fig 12, disclosing GC’s extending in the Y direction); a gate insulation pattern on a sidewall in the first direction of each of the gate electrodes (see CG, see also, fig 4 reproduced below and para [0140] disclosing insulating sidewalls and gate);
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a channel on a sidewall in the first direction of the gate insulation pattern (see fig 12 below, where channel below 12 contacts sidewalls of spacers and CS), the channel contacting a corresponding one of the bit lines (see fig 12, disclosing V1, V2 and C1-3 reaching channel to where TR7 points);
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a landing pad on the channel (see fig. 16 disclosed below, disclosing channel with landing pads at T8 and T4, dotted lines being channels);
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and a capacitor on the landing pad (see e.g. fig 20 where CA is connects to T6, Channel through the gate electrode, para [0187]), wherein the BLSA circuit pattern and the column circuit pattern overlap the cell array in a third direction substantially perpendicular to the first and second directions (see fig 19,w here WLSW and sense amplifier overlap the memory cell array).
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Regarding claim 2, Maejima discloses the semiconductor device according to claim 1, wherein the column circuit pattern includes at least one of a column decoder (see 16, fig 1), a column select line (CSL) driver (see BLKn), an input/output sense amplifier (I/O SA) (SR), or a write driver (15).
Regarding claim 3, Maejima discloses the semiconductor device according to claim 2, wherein the column circuit pattern includes the CSL driver(fig 5, 15), and wherein the semiconductor device further comprises a CSL extending in the first direction under the cell array, the CSL being electrically connected to the CSL driver (see 15 is connected to 16, 10).
Regarding claim 4, Maejima discloses the semiconductor device according to claim 2, wherein the column circuit pattern includes the I/O SA, and wherein the semiconductor device further comprises a global I/O line extending in the first direction over the cell array, the global I/O line being electrically connected to the I/O SA (see fig 5, 6 disclosing global signal lines).
Regarding claim 5, Maejima discloses the semiconductor device according to claim 1, wherein: mats are arranged in the first direction on a bank region of the substrate (see fig 6 disclosing device areas), wherein the cell array is one of a plurality of cell arrays (see fig 6 disclosing multiple arrays), and each of the mats includes a respective cell array among the plurality of cell arrays (see fig 6, disclosing multiple arrays), the mats include first mats and second mats, the second mats being at opposite end portions of the bank region in the first direction, and the column circuit pattern is in at least one of the second mats(see fig 6, disclosing multiple arrays).
Regarding claim 6, Maejima discloses the semiconductor device according to claim 5, wherein the BLSA circuit patterns are at opposing first side portions (see SR near side portions of XR), respectively, in the first direction of each of the first mats (see SR near side portions of XR), and wherein the BLSA circuit pattern and the column circuit pattern are at opposing second side portions (see XR2 and SR are on opposing sides), respectively, in the first direction of each of the second mats, and the column circuit pattern is between the BLSA circuit pattern and a peripheral circuit region of the substrate.
Regarding claim 7, Maejima discloses the semiconductor device according to claim 5, wherein the column circuit pattern includes a column select line (CSL) driver (see BLKn), and wherein the semiconductor device further comprises a CSL extending in the first direction through the first and second mats under the cell array, the CSL being electrically connected to the CSL driver (see fig 5 disclosing interconnection of CSL).
Regarding claim 8, Maejima discloses the semiconductor device according to claim 7, further comprising a global CSL continuously extending through the first and second mats in the first direction over the cell array, the global CSL being electrically connected to the CSL.
Regarding claim 9, Maejima discloses the semiconductor device according to claim 5, wherein the column circuit pattern includes an input/output sense amplifier (I/O SA), and wherein the semiconductor device further comprises a global I/O line continuously extending through the first and second mats in the first direction over the cell array, the global I/O line being electrically connected to the I/O SA (see fig 5 disclosing connections to Sense amplifier and IO connections).
Regarding claim 10, Maejima discloses the semiconductor device according to claim 9, wherein the I/O SA partially overlaps the cell array in the third direction, and wherein the I/O SA and the global I/O line are electrically connected to each other through a conductive structure in an area that is not overlapping the cell array in the third direction(see fig 5 disclosing connections to Sense amplifier and IO connections).
Regarding claim 11, Maejima discloses a semiconductor device comprising: mats arranged in a first direction on a substrate (see fig 6 disclosing placement of devices on a X/Y plane); a bit line sense amplifier (BLSA) circuit pattern in each of the mats (see figs 18 and19 disclosing Sense amplifier module on lower plane); and a cell array on the BLSA circuit pattern in each of the mats (see figs 18 and 19 disclosing WLSW), the cell array including: bit lines spaced apart from each other in a second direction crossing the first direction (see BL in the Z direction, see figs 18), each of the bit lines extending in the first direction (see figs 18 and 19 where bit lines arranged along Z direction); gate electrodes spaced apart from each other in the first direction (see fig 12, disclosing gate conductors GC spaced apart from each other), each of the gate electrodes extending in the second direction on the bit lines(see fig 12, disclosing GC’s extending in the Y direction); a gate insulation pattern on a sidewall in the first direction of each of the gate electrodes(see CG, see also, fig 4 reproduced below and para [0140] disclosing insulating sidewalls and gate);
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a channel on a sidewall in the first direction of the gate insulation pattern, the channel contacting a corresponding one of the bit lines(see fig 12 below, where channel below 12 contacts sidewalls of spacers and CS);
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a landing pad on the channel(see fig. 16 disclosed below, disclosing channel with landing pads at T8 and T4, dotted lines being channels);
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and a capacitor on the landing pad(see e.g. fig 20 where CA is connects to T6, Channel through the gate electrode), wherein the mats include first mats and second mats, the second mats being at opposite end portions (see fig 6 disclosing all the mats are arranged adjacent to one another), respectively, in the first direction, and wherein the semiconductor device further comprises a column circuit pattern under the cell array in each of the second mats, the column circuit pattern overlapping the cell array in a third direction that is substantially perpendicular to the first and second directions(see fig 19,w here WLSW and sense amplifier overlap the memory cell array).
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Regarding claim 12, Maejima discloses the semiconductor device according to claim 11, wherein the mats are on a bank region of the substrate (see fig 6, disclosing mats located in and around peripheral regions), wherein the BLSA circuit patterns are at opposing first side portions (see sense amplification regions), respectively, in the first direction of each of the first mats, and wherein the BLSA circuit pattern and the column circuit pattern are at opposing second side portions (see symmetrical arrangement in fig 6), respectively, in the first direction of each of the second mats, and the column circuit pattern is between the BLSA circuit pattern and a peripheral circuit region of the substrate (see fig 6).
Regarding claim 13, Maejima discloses the semiconductor device according to claim 11, wherein the column circuit pattern includes at least one of a column decoder, a column select line (CSL) driver, an input/output sense amplifier (I/O SA), or a write driver (see figs 6 and 7 disclosing I/O drivers wit sense amplifiers).
Regarding claim 14, Maejima discloses the semiconductor device according to claim 13, wherein the column circuit pattern includes the CSL driver, and wherein the semiconductor device further comprises a CSL continuously extending in the first direction through the first and second mats under the cell array (see figs 5 and 6 disclosing continuous extension of CSL through the mats), the CSL being electrically connected to the CSL driver (see figs 5 and 6).
Regarding claim 15, Maejima discloses the semiconductor device according to claim 14, further comprising a global CSL continuously extending in the first direction through the first and second mats over the cell array, the global CSL being electrically connected to the CSL (see fig s5 and 6 disclosing the different device areas/ mats and fig 5 disclosing the interconnections).
Regarding claim 16, Maejima discloses the semiconductor device according to claim 13, wherein the column circuit pattern includes the I/O SA (see sense amplification in figs 5, 6, and 18 ), and wherein the semiconductor device further comprises a global I/O line continuously extending in the first direction through the first and second mats over the cell array (see figs 5 and 6 disclosing I/o lines in the signal lines), the global I/O line being electrically connected to the I/O SA (see fig 5 disclosing connections).
Regarding claim 17, Maejima discloses the semiconductor device according to claim 16, wherein the I/O SA partially overlaps the cell array in the third direction (see figs 6 and 7 disclosing overlapping IO signal lines), and wherein the I/O SA and the global I/O line are electrically connected to each other through a conductive structure in an area that is not overlapping the cell array in the third direction (see fig 5, disclosing overlapping signal lines to the memory device region).
Regarding claim 18, Maejima discloses a semiconductor device comprising: first and second mats on a bank region of a substrate (see HR1, HR2, XR1, XR2, PR1, PR2 etc. having bank regions on left and right side, see i.e. Fig. 6), the substrate including the bank region (HR/XR regions) and a peripheral circuit region (PR1/PR1, see fig. 6), the first and second mats being arranged on the bank region in first and second directions crossing each other (see the regions in fig 6 arranged perpendicular to each other); first bit line sense amplifier (BLSA, see sense amplifier) circuit patterns at opposing first side portions (see fig 19 reproduced above disclosing R1, R2 on opposing sides of SR), respectively, in the first direction in each of the first mats (mats across the X direction, see fig 6); a first cell array on the first BLSA circuit patterns in each of the first mats (see Memory cell array 10, fig 19 and fig 6); a second BLSA circuit pattern and a column circuit pattern at opposing second side portions (see fig 6 disclosing multiple SR regions, see fig 6), respectively, in the first direction in each of the second mats (see fig 6); and a second cell array on the second BLSA circuit pattern and the column circuit pattern in each of the second mats (see fig 6disclosing multiple SR and h/XR), wherein the column circuit pattern overlaps the second cell array in a third direction that is substantially perpendicular to the first and second directions (see fig 6 disclosing overlap of MR and SR in the z direction and arranged in x-y direction).
Regarding claim 19, Maejima discloses the semiconductor device according to claim 18, wherein each of the second mats is arranged adjacent to the peripheral circuit region in the first direction (see fig 6, disclosing mats arranged along XY plane) such that the column circuit pattern is between the second BLSA circuit pattern and the peripheral circuit region (see fig 6 where SR regions are between Peri and Hr/Xr regions).
Regarding claim 20, Maejima discloses the semiconductor device according to claim 18, wherein the column circuit pattern includes at least one of a column decoder (see 16, fig 1), a column select line (CSL) driver (see BLKn), an input/output sense amplifier (I/O SA) (SR), or a write driver (15).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893