Prosecution Insights
Last updated: April 19, 2026
Application No. 18/448,296

PACKAGED MEMORY DEVICE WITH OVERHANG SUPPORT STRUCTURE

Final Rejection §102§103§112
Filed
Aug 11, 2023
Examiner
ANDERSON, WILLIAM H
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sandisk Technologies Inc.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
169 granted / 197 resolved
+17.8% vs TC avg
Moderate +15% lift
Without
With
+14.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
49 currently pending
Career history
246
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.9%
+6.9% vs TC avg
§102
26.7%
-13.3% vs TC avg
§112
23.3%
-16.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 197 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 (and dependent claims 2-10 dependent therefrom) and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the controller die” in line2-13. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 1 is interpreted in the instant Office action as follows: “the controller die” is equivalent to “a controller die”. This interpretation is to be confirmed by applicant in the next office action. Regarding claim 10, “a controller die” in line 2 is unclear whether it is referring to the same controller die recited in claim 1 or some other controller die. For the sake of compact prosecution, claim 10 is interpreted in the instant Office action as follows: “a controller die” in line 2 is referring to the same controller die and is equivalent to “the controller die” based on Fig. 2. This interpretation is to be confirmed by applicant in next office action. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 11-14, 16-17, and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Che (US 20240274580 A1). Regarding independent claim 11, Che discloses a memory device (Fig. 1), comprising: a substrate (110); a plurality of silicon dies (115-1, 115-2, 115-3; [0021]: “through-silicon vias” requires these dies to include silicon) attached one atop another (atop in the y direction) in an offset manner (offset in the x direction), wherein a bottom one of the silicon dies (115-1) is attached to the substrate, wherein a second one of the silicon dies (115-3) is situated above the bottom one of the silicon dies (above in the y direction), the second one of the silicon dies including an overhang portion (155-3) that hangs beyond (beyond in the x direction) each other silicon die included in the plurality of silicon dies; and a printed support structure (145; [0083]: “a three-dimensional printing operation”) attached to the substrate, the printed support structure supporting the overhang portion of the second one of the silicon dies (supporting in the y direction). Illustrated below is Fig. 1 of Che. PNG media_image1.png 503 757 media_image1.png Greyscale Regarding claim 12: Che discloses the memory device of claim 11 (Fig. 1), wherein a third one of the silicon dies (115-2) is situated between (between in the y direction) the bottom one of the silicon dies and the second one of the silicon dies, and wherein the printed support structure supports (supports in the y direction) a second overhang portion (155-2) of the third one of the silicon dies. Regarding claim 13, Che discloses the memory device of claim 11 (Fig. 1), wherein a third one of the silicon dies (115-2) is situated between (between in the y direction) the bottom one of the silicon dies and the second one of the silicon dies, and wherein a second printed support structure (a portion of 145) supports the third one of the silicon dies (supports in the y direction). Regarding claim 14, Che discloses the memory device of claim 11 (Fig. 1), wherein the printed support structure is composed of an elastomeric material ([0043]: “a compliant material”). Regarding independent claim 16, Che discloses a method of assembling a memory device (Fig. 1), the method comprising: printing a support structure (145; [0083]: “a three-dimensional printing operation”) onto a substrate (110); stacking a plurality of silicon dies (115; [0021]: “through-silicon vias” requires these dies to include silicon) on the substrate (stacked in the y direction), the stack of silicon dies including a first silicon die (115-1) contacting the substrate and a second silicon die (115-3) situated above the first silicon die (above in the y direction) and offset from the first silicon die in a lateral direction (offset in the x direction) to form an offset portion (155-3), wherein the offset portion of the second silicon die is supported (supported in the y direction) by the support structure; and electrically connecting each silicon die included in the stack of silicon dies to the substrate with one or more bond wires (not shown; [0025]: “wire bonding”). Regarding claim 17, Che discloses the method of claim 16 (Fig. 1), further comprising: attaching a controller die (105-1; [0064]: “a microcontroller”) to the substrate, wherein the controller die is in electrical communication with each silicon die included in the stack of silicon dies by way of the substrate ([0046]: “integrated circuit 105-1 is communicatively coupled to the integrated circuits 105-2 and 105-3 through the substrate 110”). Regarding claim 19, Che discloses the method of claim 16 (Fig. 1), wherein the stack of silicon dies includes a third silicon die (115-2) situated between (between in the y direction) the first silicon die and the second silicon die, and wherein the third silicon die is supported (supported in the y direction) by the support structure. Regarding claim 20, Che discloses the method of claim 16 (Fig. 1), further comprising printing a second support structure onto the substrate (a portion of 145), wherein the stack of silicon dies includes a third silicon die (115-2) situated between (between in the y direction) the first silicon die and the second silicon die, and wherein the third silicon die is supported by the second support structure (supported in the y direction). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 20110079890 A1) in view of Che. Regarding claim 1 as noted in the 112(b) rejection, Song discloses a memory device (Fig. 12) comprising: a substrate (111); a memory die stack including: a [first die] (136) having a first contact pad surface (See annotated figure) and a bottom surface (See annotated figure) attached to the substrate (attached by 133); and a [second die] (196) stacked on the [first die] (stacked in the z direction), the [second die] including a second contact pad surface (See annotated figure), wherein an overhang portion of the [second die] (See annotated figure) extends beyond the [first die] (extends beyond in the x direction); a [support structure] (a portion of 123, See reference lines in annotated figure) attached to the substrate, the [support structure] supporting the overhang portion of the [second die] (supporting in the z direction); and one or more bond wires (175) that electrically connect the first and second contact pad surfaces to the substrate (connected at 114/118), thereby electrically connecting the [first and second dies] to a controller die ([0245]: “a non-memory device and/or a memory device in order to perform a storage function”) by way of the substrate (there are no other electrical connections for the dies, thus connection to the controller must be “by way of the substrate”). Illustrated below is Fig. 12 of Song. PNG media_image2.png 476 748 media_image2.png Greyscale Song fails to teach the specific process of forming the support structure. Thus, Song fails to teach “a printed support structure”. Che teaches a process of forming a support structure ([0083]: “forming the terraced support structure comprises”) includes printing ([0087]: “a three-dimensional printing operation”). The process of Che is relevant to the support structure of Song because in each case the process forms a support structure (Che: [0083]: “terraced support structure”; Song: [0154]: “physically supported by the first auxiliary structure 123”). Thus, a person of ordinary skill in the art before the effective filing date would have had predictable results using the process of Che to print the support structure of Song, because in each case a support structure is formed. Doing so would arrive at the claimed printed support structure. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed printed support structure because it is formed using a known technique in a similar way. MPEP 2143 (I)(C). Song in view of Che as applied above fails to teach specific materials useful for the first and second dies. Thus, Song and Che fail to teach “a first silicon die” and “a second silicon die”. However, Che discloses first and second dies (Fig. 1: 115-1, 115-3), and teaches these dies may include silicon ([0021]: “through-silicon vias” requires these dies to include silicon). Che and Song are related because each discloses stacked memory dies (Che: [0033]: “non-volatile memory”; Song: [0137]: “a non-volatile memory device”). A person of ordinary skill in the art before the effective filing date could have modified the material of the first and second dies (of Song) to include silicon (as taught by Che). Doing so would arrive at the claimed die material configuration. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration of the first and second dies because it is a configuration known suitable for memory dies. MPEP 2143 (I)(E). Regarding claim 2, Song in view of Che discloses the memory device of claim 1 (Song: Fig. 12), wherein the first and second silicon dies comprise memory dies ([0137]: “a non-volatile memory device”). Regarding claim 3, Song in view of Che discloses the memory device of claim 2 (Song: Fig. 12), wherein the first and second silicon dies comprise NAND dies (Che: [0033]: “non-volatile memory 205 may include NAND memory”). Regarding claim 4, Song in view of Che discloses the memory device of claim 1 (Song: Fig. 12), wherein the memory die stack includes: a third silicon die (146) including a third contact pad surface (See annotated figure), the third silicon die situated between the first silicon die and the second silicon die, wherein the third silicon die is supported by the printed support structure. Regarding claim 5, Son in view of Che discloses the memory device of claim 1 (Song: Fig. 12), wherein the memory die stack includes: a third silicon die (146) including a third contact pad surface (See annotated figure), the third silicon die situated between the first silicon die and the second silicon die (between in the z direction), wherein the third silicon die is supported by a second printed support structure (a different portion and shape of 123, See reference lines in annotated figure). Regarding claim 6, Song in view of Che discloses the memory device of claim 1 (Song: Fig. 12), wherein the printed support structure is composed of an elastomeric material (Song: [0169]: “a sol or gel type insulating material”; Che: [0043]: “a compliant material”). Regarding claim 7, Song in view of Che discloses the memory device of claim 1 (Song: Fig. 12), wherein the printed support structure is printed directly onto the substrate (123 is directly on 111). Regarding claim 8, Song in view of Che discloses the memory device of claim 1 (Song: Fig. 12), wherein the first silicon die and the second silicon die each have a thickness (thickness in the z direction) […]. Song in view of Che fails to teach a specific thickness range for the first and second silicon dies. Thus, Song in view of Che as applied above fails to teach “the first silicon die and the second silicon die each have a thickness of less than 40 microns”. Che teaches a thickness range for the first and second silicon dies ([0022]: “less than approximately 40 microns”). The thickness range of Che is relevant to the first and second silicon dies of Song because in each case the dies are memory dies (Song: [0137]: “a non-volatile memory device”; Che: [0033]: “non-volatile memory 205 may include NAND memory”). Modifying the thicknesses of the first and second silicon dies of Song and Che by incorporating the thickness range of Che would arrive at the claimed thickness configuration (a size). A person of ordinary skill in the art before the effective filing date would have been motivated to do so to produce a memory die. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed thickness configuration because it is a memory die size configuration known within prior art. MPEP 2144.04 (IV)(A). Regarding claim 9, Song in view of Che discloses the memory device of claim 8 (Song: Fig. 12), wherein the first silicon die and the second silicon die each have a thickness of less than 36 microns (Che: [0022]: “less than approximately 40 microns”). Regarding claim 10 as noted in the 112(b) rejection, Song in view of Che discloses the memory device of claim 1, further comprising: the controller die ([0245]: “a non-memory device and/or a memory device in order to perform a storage function”) […]. Song in view of Che as applied above teaches the controller die, but fails to teach the structural configuration of the controller die. Thus, Song in view of Che fails to teach “a controller die mounted on the substrate adjacent to the memory die stack; a plurality of solder bumps that attach and electrically connect the controller die to the substrate; and underfill disposed beneath the controller die”. However, Che teaches a controller die (Fig. 1: 105-1; [0064]: “a microcontroller”) mounted on the substrate (110) adjacent to the memory die stack (105-2); a plurality of solder bumps ([0046]: “a bumped die that is joined to the substrate 110 using a surface mount (SMT) process”) that attach and electrically connect the controller die to the substrate; and underfill ([0046]: “an underfill material 305 (e.g., an epoxy polymer) may be between the integrated circuit 105-1 and the substrate 110”) disposed beneath the controller die. Modifying the structural configuration of Song’s controller die by incorporating the structural configuration disclosed by Che would arrive at the claimed controller die configuration. One of ordinary skill in the art before the effective filing date would have been motivated to do so because Che teaches this configuration having the design incentive of enabling communication between the controller die and the memory die stack ([0046]: “integrated circuit 105-1 is communicatively coupled to the integrated circuits 105-2 and 105-3 through the substrate 110”). This design incentive is consistent with the required controller die functionality of Song ([0245]: “to perform a storage function”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed controller die configuration because it would enable functionally configuring the controller die with the memory stack. MPEP 2143 (I)(F). Regarding independent claim 11, Song discloses a memory device (Fig. 12), comprising: a substrate (111); a plurality of [dies] (136/146/156/166/196/206/216/226) attached one atop another (atop in the z direction) in an offset manner (offset in the x direction), wherein a bottom one of the [dies] (136) is attached to the substrate, wherein a second one of the [dies] (196) is situated above the bottom one of the [dies] (above in the z direction), the second one of the [dies] including an overhang portion (See annotated figure) that hangs beyond (beyond in the x direction) each other [die] included in the plurality of [dies]; and a [support structure] (a portion of 123, See reference lines in annotated figure) attached to the substrate, the [support structure] supporting the overhang portion of the second one of the [dies] (supporting in the z direction). Song fails to teach the specific process of forming the support structure. Thus, Song fails to teach “a printed support structure”. Che teaches a process of forming a support structure ([0083]: “forming the terraced support structure comprises”) includes printing ([0087]: “a three-dimensional printing operation”). The process of Che is relevant to the support structure of Song because in each case the process forms a support structure (Che: [0083]: “terraced support structure”; Song: [0154]: “physically supported by the first auxiliary structure 123”). Thus, a person of ordinary skill in the art before the effective filing date would have had predictable results using the process of Che to print the support structure of Song, because in each case a support structure is formed. Doing so would arrive at the claimed printed support structure. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed printed support structure because it is formed using a known technique in a similar way. MPEP 2143 (I)(C). Song in view of Che as applied above fails to teach specific materials useful for the plurality of dies. Thus, Song and Che fail to teach “a plurality of silicon dies”. However, Che discloses a plurality of dies (Fig. 1: 115), and teaches these dies may include silicon ([0021]: “through-silicon vias” requires these dies to include silicon). Che and Song are related because each discloses stacked memory dies (Che: [0033]: “non-volatile memory”; Song: [0137]: “a non-volatile memory device”). A person of ordinary skill in the art before the effective filing date could have modified the material of the plurality of dies (of Song) to include silicon (as taught by Che). Doing so would arrive at the claimed die material configuration. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed material configuration of the plurality of dies because it is a configuration known suitable for memory dies. MPEP 2143 (I)(E). Regarding claim 15, Song in view of Che discloses the memory device of claim 11 (Song: Fig. 12), wherein the plurality of silicon dies includes at least eight silicon dies (eight are shown), and wherein the printed support structure supports half of the plurality of silicon dies (half of the dies, i.e., 4 dies, are inclusive within the number of dies supported by 123). Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Che as applied to claim 16 above, and further in view of Song and Benrashid (US 20050022697 A1). Regarding claim 18, Che discloses the method of claim 16, however, fails to teach the method “further comprising: curing the support structure with an ultraviolet light source”. Song teaches a support structure (Fig. 12: 123) and teaches the material of the support structure may include sol gel ([0169]: “structure 123 may include a sol or gel type insulating material”). Song fails to teach a method of curing the sol gel. Benrashid discloses a method of curing sol gel comprising: curing the material with an ultraviolet light source ([0025]: “UV curable”). The method of Benrashid is relevant to the method of Song because in each case a sol gel material is formed on a substrate (Benrashid: [0025]: “useful for printing different structures on top of electronic and/or optoelectronic wafers”; Song: [0153]: “auxiliary structure 123 may be adhered to the substrate”). Incorporating the teachings of Benrashid (UV curing) and Song (a sol gel material) when forming the support structure of Che would arrive at the claimed support structure. Benrashid provides a teaching to motivate one to cure the support structure with an ultraviolet light source in that it would produce a support structure having improved cracking characteristics (Benrashid: [0025]: “improved cracking”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed support structure method because it would improve cracking characteristics. MPEP 2143 (I)(G). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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Prosecution Timeline

Aug 11, 2023
Application Filed
Dec 23, 2025
Non-Final Rejection — §102, §103, §112
Mar 12, 2026
Examiner Interview Summary
Mar 12, 2026
Applicant Interview (Telephonic)
Mar 26, 2026
Response Filed
Apr 14, 2026
Final Rejection — §102, §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+14.9%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 197 resolved cases by this examiner. Grant probability derived from career allow rate.

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