DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-8 and 16-26 are pending.
Claims 21-26 are new.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-8 and 16-20, in the reply filed on 01/06/2026 is acknowledged. Additionally, applicant elects new claims 21-26, drawn to Group I.
Group II claims 9-14, are withdrawn and cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method. Election was made without traverse in the reply filed on 01/06/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/11/2023 has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
DOUBLE-SIDED JANUS TRANSITION METAL DICHALCHOGENIDE CMOS DEVICE AND MANUFACTURING METHOD THEREOF
Claim Objections
Claims 17 and 24 are objected to because of the following informalities:
Claim 17, line 4, should read “second gate structure overlaps a channel region of the Janus transition metal dichalcogenide”
Claim 24, line 1 should read “The method of claim 23, wherein the two first contacts and the two second contacts”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ding et al. (First-Principles Predictions of Janus MoSSe and WSSe for FET Applications; herein known as Ding).
Regarding claim 1, Ding teaches (annotated Fig. 2 below, ([3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]) an integrated circuit device, comprising: a Janus transition metal dichalcogenide layer (Janus TMD) having opposite first (S1) and second sides (S2); a first gate structure (Bottom gate) on the first side of the Janus transition metal dichalcogenide layer; and a second gate structure (Top gate) on the second side of the Janus transition metal dichalcogenide layer.
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Regarding claim 7, Ding teaches (Figure 1a, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]) the integrated circuit device of claim 1, wherein the Janus transition metal dichalcogenide layer (Figure 1a) has a first chalcogen atom (S) adjacent the first side (Mo) and a second chalcogen atom (Se) adjacent the second side, and the second chalcogen atom is different from the first chalcogen atom ([1. Introduction, paragraph 3]). A material containing a first chalcogen atom adjacent the first side of a metal core layer, and a second, different, chalcogen atom adjacent the second side of the core layer is the definition of a Janus transition metal dichalcogenide material, and thus the Janus transition metal dichalcogenide layer must necessarily contain this structure.
Regarding claim 8, Ding teaches (Figure 1a, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]) the integrated circuit device of claim 1, wherein the Janus transition metal dichalcogenide layer is a MoSSe layer ([3.2 Performances of Janus MoSSe and WSSe MOSFETs]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ding as applied to claim 1 above, and further in view of Lau et al. (Dielectrics for Two-Dimensional Transition-Metal Dichalcogenide Applications; herein known as Lau).
Regarding claim 4, Ding teaches the integrated circuit device of claim 1 wherein the first gate structure comprises a dielectric layer (Oxide, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 1]) but does not explicitly teach wherein it is a high-k dielectric layer.
Lau teaches wherein the dielectric layer is a high-k dielectric layer ([Page 4, Scalability]).
Because Ding and Lau are directed toward TMD device optimization, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ding in view of Yuan and Lau to include a high-k dielectric layer for improved scalability by decreased equivalent oxide thickness, achieved by use of a high-k dielectric material (Lau, [Page 4, Scalability]).
Claims 1, 5, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ding in view of Yuan (US PGPub 2010/0327355; herein known as Yuan).
Regarding claim 1, Ding teaches (Annotated Fig. 2 below) an integrated circuit device, comprising: a Janus transition metal dichalcogenide layer (Janus TMD) having opposite first (S1) and second sides (S2); a first gate structure (Bottom gate) on the first side of the Janus transition metal dichalcogenide layer ([3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]).
Ding does not explicitly teach a second gate structure on the second side of the Janus transition metal dichalcogenide layer.
Yuan teaches (Fig. 3) a double-sided CMOS including a second gate structure (317, [0037]) on the second side of the channel layer (304, [0037]).
Because Ding and Yuan are both directed toward CMOS TFTs, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ding and of Yuan to include a second gate structure on the second side of the Janus transition metal dichalcogenide layer in order to provide high transistor density (Yuan, [0006]).
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Regarding claim 5, Ding in view of Yuan teaches (Ding, annotated Fig. 2 above, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]) the integrated circuit device of claim 1, further comprising: a third gate structure (Top gate) on the second side (S2) of the Janus transition metal dichalcogenide layer (Janus TMD), wherein the third gate structure vertically overlaps the first gate structure (Bottom gate).
Regarding claim 7, Ding in view of Yuan teaches (Ding, Figure 1a, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]) the integrated circuit device of claim 1, wherein the Janus transition metal dichalcogenide layer (Figure 1a) has a first chalcogen atom (S) adjacent the first side (Mo) and a second chalcogen atom (Se) adjacent the second side, and the second chalcogen atom is different from the first chalcogen atom ([1. Introduction, paragraph 3]).
Regarding claim 8, Ding in view of Yuan teaches (Ding, Figure 1a, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]) the integrated circuit device of claim 1, wherein the Janus transition metal dichalcogenide layer is a MoSSe layer ([3.2 Performances of Janus MoSSe and WSSe MOSFETs]).
Claims 2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Ding in view of Yuan as applied to claim 1 above, and further in view of Arava et al. (US PGPub 2021/0288152; herein known as Arava).
Regarding claim 2, Ding in view of Yuan teaches (annotated Fig. 2 below, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 2]), the integrated circuit device of claim 1, further comprising: two first contacts (not pictured, described as being at the end side of UL at the source or drain, designated by C11 and C12) in contact with the second side of the Janus transition metal dichalcogenide layer, wherein the first contacts are at opposite sides of a first channel portion (Lch) of the Janus transition metal dichalcogenide layer overlapping the first gate structure (Bottom gate).
Ding in view of Yuan does not explicitly teach two second contacts in contact with the first side of the Janus transition metal dichalcogenide layer, wherein the second contacts are at opposite sides of a second channel portion of the Janus transition metal dichalcogenide layer overlapping the second gate structure.
Arava teaches combination of an MoSe2 PMOS and an MoS2 NMOS transistor to create a CMOS inverter. Because Ding in view of Yuan and Arava are directed toward CMOS TFTS, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ding in view of Yuan and of Arava to utilize a material capable of forming both a PMOS structure on the p-type Gate-Se-Mo material side, and an NMOS transistor on the Gate-S-Mo material side of the Janus TMD, in order to form a high density CMOS device to achieve heterogenous integration (Arava, [0049]).
Ding in view of Yuan and Arava does not explicitly teach two second contacts in contact with the first side of the Janus transition metal dichalcogenide layer, wherein the second contacts are at opposite sides of a second channel portion of the Janus transition metal dichalcogenide layer overlapping the second gate structure.
Yuan further teaches (Fig. 3) a double-sided CMOS, with an NMOS on one substrate side, and a PMOS on the opposite side.
It would have been obvious to further combine the teachings of Ding in view of Yuan and Arava to utilize the TFT gate structure of Ding for the double-sided CMOS of Yuan, to have a top gate and corresponding back gate and second contacts in contact with the first side of the Janus transition metal dichalcogenide layer, wherein the second contacts are at opposite sides of a second channel portion of the Janus transition metal dichalcogenide layer overlapping the second gate structure to therefore form a CMOS device, in order to provide high transistor density on a single substrate (Yuan, [0006]).
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Regarding claim 6, Ding in view of Yuan teaches the integrated circuit device of claim 1, but does not explicitly teach further comprising: a fourth gate structure on the first side of the Janus transition metal dichalcogenide layer, wherein the fourth gate structure vertically overlaps the second gate structure.
Arava teaches combination of an MoSe2 PMOS and an MoS2 NMOS transistor to create a CMOS inverter. One of ordinary skill in the art would then understand that a Janus TMD material, for example MoSSe, would be able to form a PMOS on the Gate-Se-Mo material side, and an NMOS transistor on the Gate-S-Mo material side of the Janus TMD.
Yuan teaches (Fig. 3) a double-sided CMOS, with an NMOS on one substrate side, and a PMOS on the opposite side.
It would have been obvious to combine the teachings of Ding, Yuan, and Arava to utilize the TFT gate structure of Ding for the double-sided CMOS of Yuan, to have a corresponding back gate for the second gate structure, i.e., a fourth gate structure on the first side of the Janus transition metal dichalcogenide layer, wherein the fourth gate structure vertically overlaps the second gate structure, therefore forming a CMOS device, in order to provide high transistor density on a single substrate (Yuan, [0006]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ding in view of Yuan and Arava, as applied to claim 2 above, and further in view of Zhao et al. (Performance Upper Limit of Sub-10 nm Monolayer MoS2 Transistors with MoS2–Mo Electrodes; herein known as Zhao).
Regarding claim 3, Ding in view of Yuan and Arava teaches the integrated circuit device of claim 2, but does not explicitly teach wherein the first and second contacts comprise a same conductive material.
Zhao teaches (Fig. 2a) wherein the first and second contacts (Sources and drains) comprise a same conductive material (Figure 1d).
Because Ding in view of Yuan and Arava and Zhao are directed toward Janus TMD FET construction, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ding in view of Yuan and Arava and Zhao in order to reduce the interlayer distance between the Se-metal layer and the S-metal layer, creating strong bonding (Zhao, [3.1 Interlayer Distance and Charge Transfer]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ding in view of Yuan as applied to claim 1 above, and further in view of Lau.
Regarding claim 4, Ding in view of Yuan teaches the integrated circuit device of claim 1 wherein the first gate structure comprises a dielectric layer (Oxide, [3.2 Performances of Janus MoSSe and WSSe MOSFETs, paragraph 1]) but does not explicitly teach wherein it is a high-k dielectric layer.
Lau teaches wherein the dielectric layer is a high-k dielectric layer ([Page 4, Scalability]).
Because Ding in view of Yuan and Lau are directed toward TMD device optimization, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ding in view of Yuan and Lau to include a high-k dielectric layer for improved scalability by decreased equivalent oxide thickness, achieved by use of a high-k dielectric material (Lau, [Page 4, Scalability]).
Allowable Subject Matter
The following is an examiner’s statement of reasons for allowance:
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Claims 15-26 are allowed.
Regarding claim 15, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a method for fabricating an integrated circuit device, comprising: forming two second contacts over a second substrate; and placing a Janus transition metal dichalcogenide layer between the first and second substrates.
Kumari et al. (A detailed investigation of dielectric-modulated dual-gate TMD FET based label-free biosensor via analytical modelling; herein known as Kumari), teaches (Figure 3) a method for fabricating an integrated circuit device wherein a gate is formed over a first substrate and a TMD layer is placed over the first substrate, but teaches wherein upper gate layers are deposited on top of the TMD layer, not forming a second gate structure over a second substrate and placing the Janus TMD between the first and second substrates. Kumari does not teach nor suggest a reason to utilize a second substrate in device manufacture and one of ordinary skill in the art would not find it obvious to modify the method of Kumari to include a second substrate with gate structures deposited on it, as it would increase process steps and cost.
Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Claims 16-20 are allowed as dependent on claim 15.
Regarding claim 21, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a method for fabricating an integrated circuit device, comprising: forming a second gate structure over a second substrate; and placing a Janus transition metal dichalcogenide layer between the first and second substrates. Kumari, teaches (Figure 3) a method for fabricating an integrated circuit device wherein a gate is formed over a first substrate and a TMD layer is placed over the first substrate, but teaches wherein upper gate layers are deposited on top of the TMD layer, not forming a second gate structure over a second substrate and placing the Janus TMD between the first and second substrates. Kumari does not teach nor suggest a reason to utilize a second substrate in device manufacture and one of ordinary skill in the art would not find it obvious to modify the method of Kumari to include a second substrate with gate structures deposited on it, as it would increase process steps and cost.
Prior art references alone or in combination, fail to disclose, teach, or suggest every limitation of the invention as claimed.
Claims 22-26 are allowed as dependent on claim 21.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00.
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/EMILY FARMER/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812