DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, 11, 14-15, 17, 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (U.S. Publication No. 2022/0199624 A1; hereinafter Huang)
With respect to claim 1, Huang discloses a integrated circuit device comprising: a power switch cell comprising: an upper transistor [101] on a substrate [140] (See ¶[0035]; substrate [826] in Figure 8), wherein the upper transistor comprises an upper channel region [105], first and second upper source/drain regions [106] respectively on opposing sides of the upper channel region, and an upper gate electrode [110] on the upper channel region; and a lower transistor [102] between the substrate and the upper transistor, wherein the lower transistor comprises a lower channel region [105], first and second lower source/drain regions [106] respectively on opposing sides of the lower channel region [105], and a lower gate electrode [110] on the lower channel region, wherein the first and second upper source/drain regions and the first and second lower source/drain regions have the same conductivity type (see ¶[0032]), the first upper source/drain region and the first lower source/drain region are electrically connected to each other, the second upper source/drain region and the second lower source/drain region are electrically connected to each other, and the upper gate electrode and the lower gate electrode are electrically connected to each other (See Figure 2A, 5A; ¶[0044] and ¶[0053]).
With respect to claim 2, Huang discloses wherein the upper channel region and the lower channel region are spaced apart from each other in a vertical direction and overlap each other in the vertical direction (see Figure 2A).
With respect to claim 3, Huang discloses a first conductive contact [581] contacting both the first upper source/drain region and the first lower source/drain region (see Figure 5A).
With respect to claim 8, Huang discloses wherein the lower gate electrode is a first portion of a common gate electrode, and the upper gate electrode is a second portion of the common gate electrode (See ¶[0034]).
With respect to claim 11, Huang discloses a logic circuit block, wherein the first upper source/drain region and the first lower source/drain region are electrically connected to the logic circuit block (see ¶[0026] and Figure 8).
With respect to claim 14, Huang discloses an integrated circuit device comprising: an upper transistor [101] on a substrate [140] (See ¶[0035]; substrate [826] in Figure 8), wherein the upper transistor comprises an upper channel region [105], first and second upper source/drain regions [106] respectively on opposing sides of the upper channel region, and an upper gate electrode [110]; and a lower transistor [102] between the substrate and the upper transistor, wherein the lower transistor comprises a lower channel region [105], first and second lower source/drain regions [106] respectively on opposing sides of the lower channel region, and a lower gate electrode [110], wherein the upper transistor and the lower transistor have the same conductivity type (see ¶[0032]), the first upper source/drain region and the first lower source/drain region are electrically connected to each other, and the second upper source/drain region and the second lower source/drain region are electrically connected to each other (See Figure 2A, 5A; ¶[0044] and ¶[0053]).
With respect to claim 15, Huang discloses wherein the upper channel region and the lower channel region are spaced apart from each other in a vertical direction and overlap each other in the vertical direction (see Figure 2A).
With respect to claim 17, Huang discloses wherein the upper gate electrode and the lower gate electrode are electrically connected to each other (See ¶[0034]).
With respect to claim 19, Huang discloses a method of forming an integrated circuit device, the method comprising: forming a lower transistor [102] on a substrate [140], wherein the lower transistor comprises a lower channel region [105], first and second lower source/drain regions [106] respectively on opposing sides of the lower channel region, and a lower gate electrode [110]; and forming an upper transistor [101] on the lower channel region, wherein the upper transistor comprises an upper channel region [105], first and second upper source/drain regions [106] respectively on opposing sides of the upper channel region, and an upper gate electrode [110], wherein the first lower source/drain region and the first upper source/drain region have the same conductivity type (see ¶[0032]), the first upper source/drain region and the first lower source/drain region are electrically connected to each other, and the second upper source/drain region and the second lower source/drain region are electrically connected to each other (See Figure 2A, 5A; ¶[0044] and ¶[0053]).
With respect to claim 20, Huang discloses wherein the upper gate electrode and the lower gate electrode are electrically connected to each other (See ¶[0034]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4-7, 9-10, 12-13, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Xie et al. (U.S. Publication No 2023/0345691; hereinafter Xie).
With respect to claim 4, Huang fails to disclose a first power wire that is in the substrate, wherein the first conductive contact is electrically connected to the first power wire.
In the same field of endeavor, Xie teaches a first power wire [851/741] that is in the substrate, wherein the first conductive contact is electrically connected to the first power wire (see Figure 9A-C). Implementation of a power wire as taught by Xie allows for connections between transistor structures and power devices (See ¶[0040]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 5, the combination of Huang and Xie disclose a logic circuit block, wherein the first power wire is electrically connected to the logic circuit block (see Huang ¶[0026] and ¶[0065]).
With respect to claim 6, Huang fails to disclose a second conductive contact contacting both the second upper source/drain region and the second lower source/drain region.
In the same field of endeavor, Xie teaches a second conductive contact [610] contacting both the second upper source/drain region and the second lower source/drain region (see Figure 9A-9C). Implementation of conductive contacts as taught by Xie allow for internal connections between adjacent transistor structures (see Xie ¶[0035]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 7, the combination of Huang and Xie discloses a first lower wire [731], wherein the second upper source/drain region is between the substrate [110] and the first lower wire, and the second conductive contact [610] is electrically connected to the first lower wire (see Figure 4A-4C and Figure 9C).
With respect to claim 9, Huang fails to disclose a second lower wire, wherein the upper gate electrode is between the substrate and the second lower wire, and the second lower wire is electrically connected to the upper gate electrode. In the same field of endeavor, Xie teaches a second lower wire [723], wherein the upper gate electrode [520] is between the substrate [100] and the second lower wire, and the second lower wire is electrically connected to the upper gate electrode (see Figure 4B and 9A-9C).
Connections from the second lower wire and the upper gate electrode as taught by Xie allow for power connections to be established to allow the transistor to function (see ¶[0045]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 10, Huang discloses wherein the first and second lower source/drain regions are spaced apart from each other in a first horizontal direction (see Figure 5A), but fails to disclose the integrated circuit device further comprises first and second power wires that are in the substrate and are spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction, and the first upper source/drain region and the first lower source/drain region are electrically connected to the first power wire, and the upper and lower gate electrodes overlap the second power wire in a vertical direction that is perpendicular to the first and second horizontal directions.
In the same field of endeavor, Xie teaches first [741/851] and second [871/752] power wires that are in the substrate and are spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction, and the first upper source/drain region and the first lower source/drain region are electrically connected to the first power wire, and the upper and lower gate electrodes overlap the second power wire in a vertical direction that is perpendicular to the first and second horizontal directions (See Figure 8A-8C). Implementation of power wires in the orientation as taught by Xie allows for connections between transistor structures and power devices (See ¶[0040]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, Huang fails to explicitly disclose a backside power distribution network structure (BSPDNS), wherein the first upper source/drain region and the first lower source/drain region are electrically connected to the logic circuit block through the BSPDNS, however does disclose backside interconnects and electrically connected to a logic circuit (see Figure 8; ¶[0026] and ¶[0065]). In the same field of endeavor, Xie teaches a backside power distribution network structure (BSPDNS), wherein the first upper source/drain region and the first lower source/drain region are electrically connected to the logic circuit block through the BSPDNS (See ¶[0047] and Figures 9A-9C). Implementation of a backside power distribution network structure allows for a power supply to the transistor structures of the device (see Xie ¶[0047-0048]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 13, Huang fails to disclose wherein the second upper source/drain region and the second lower source/drain region are electrically connected to a first power having a positive voltage, but does disclose a power supply connected to the transistor devices (See Claim 12). Xie teaches wherein the second upper source/drain region and the second lower source/drain region are electrically connected to a first power having a positive voltage (see Figures 9A-9C and ¶[0046-0048]).
Implementation of a power connection to the source/drain regions results in a voltage at source power supply line allowing for a pull-up/pull-down and pass gate transistor orientation (See ¶[0048]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 16, Huang fails to disclose a first power wire that is in the substrate and is electrically connected to the first upper source/drain region and the first lower source/drain region; and a first lower wire that is electrically connected to the second upper source/drain region and the second lower source/drain region, wherein the second upper source/drain region is between the substrate and the first lower wire. In the same field of endeavor, Xie teaches a first power wire [851/741] that is in the substrate and is electrically connected to the first upper source/drain region and the first lower source/drain region; and a first lower wire [731] that is electrically connected to the second upper source/drain region and the second lower source/drain region, wherein the second upper source/drain region is between the substrate and the first lower wire (See Figure 9A-9C)
Implementation of a power wire and lower wires as taught by Xie allows for connections between transistor structures and power devices (See ¶[0040] and ¶[0045]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 18, the combination of Huang and Xie discloses a second lower wire [723] that is electrically connected to the upper gate electrode and the lower gate electrode, wherein the upper gate electrode is between the substrate and the second lower wire (see Figure 4B and 9A-9C).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN LOKE can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JONATHAN HAN/Primary Examiner, Art Unit 2818