CTNF 18/448,703 CTNF 90697 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Species B, figures 4-19, claims 1-3 and 21-25 in the reply filed on March 24, 2025 is acknowledged. Accordingly, claims 4-20 have been withdrawn from consideration. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on September 6, 2023 was considered by the examiner. Drawing Objections 06-31 AIA The extensive drawings have not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings. Specification Objections 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. 07-29 AIA The disclosure is objected to because of the following informalities: In ¶ 0029, Applicant needs to add “(not shown)” after the peripheral circuit and other elements not shown in figure 3. In addition, Applicant needs to add “(not shown)” after the discussion of the Pch-Fet and Nch-Fet. In ¶ 0053, there are a plurality of elements which are not shown in the figures, and thus, “(not shown)” needs to be added after them . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sawabe et al. (US 2019/0296155 A1) (“Sawabe”), in view of Juengling (US 2019/0067288 A1) (“Juengling”) . Regarding claim 1, Sawabe teaches at least in figures 12, 14, and 16: a semiconductor substrate (while no substrate is disclosed in Sawabe it is extremely obvious that one would create the device of Sawabe on a substrate); a capacitor (71-73) above the semiconductor substrate (as stated above it would be obvious that 71-73 would be built above a semiconductor substrate), the capacitor (71-73) extending in a first direction (first direction; hereinafter “A”) and including a first electrode (71 or 72) and a second electrode (72 or 71) facing the first electrode (71 or 72); a first conductive layer (18) above the capacitor (71-73) in the first direction (A) and extending in a second direction (second direction; hereinafter “B”) intersecting the first direction (A); a semiconductor layer (16) penetrating the first conductive layer (18) in the first direction (A) and electrically connected to the first electrode (16 is electrically connected to 71 or 72 by means of 14/62); a first insulating film (22/20) between the first conductive layer (18) and the semiconductor layer (16). Sawabe does not teach: a first conductor above or below the first conductive layer in the first direction and electrically connected to the first conductive layer; a second conductive layer extending in the second direction and electrically connected to the first conductive layer via the first conductor. This is because Sawabe does not teach the electrical connection to the gate or WL. Juengling teaches at least in figures 2-3, and 6: a first conductor (71) above or below the first conductive layer in the first direction (vertical or A) and electrically connected to the first conductive layer (52/32); a second conductive layer (58/65) extending in the second direction (horizontal direction or B) and electrically connected to the first conductive layer (38/52) via the first conductor (71). It would have been obvious to one of ordinary skill in the art to combine the two prior art references as it is obvious that in order to electrically connect the gate of the memory transistor of Sawabe one would need to bring an electrical connection down to the gate/word line by means of RDL or Mx structures. Both which include the use of horizontal lines and vias. One means to do this is contained in Juengling. Thus, the combination of references would have been obvious to one of ordinary skill in the art before the effective filing date of the current application. Regarding claim 2, Sawabe teaches at least in figures 12, 14, and 16: wherein the semiconductor layer (16) is an oxide semiconductor (¶ 0032, where IGZO can be used). Regarding claim 3, Juengling teaches at least in figures 2-3, and 6: wherein the second conductive layer (58/65) is above the first conductive layer (38/52) . 07-21-aia AIA Claim (s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sawabe, in view of Juengling, in view of Zhao, Larry, “All about interconnects”, https://semiengineering.com/all-about-interconnects/, Dec. 18, 2017 . Regarding claim 21, The limitation: a third conductive layer above the first conductive layer, the third conductive layer extending in a third direction intersecting the first and second direction and electrically connected to the semiconductor layer, is considered a duplication of parts under MPEP 2144.04(VI)(B). It is considered a duplication of parts because adding more metal layers (local interconnects or global interconnects referenced as RDL and Mx structures in claim 1) has no patentable significance. This is because there is nothing new or unexpected about adding more conductive layers. Further, if the first direction is “z”, and the second direction is “x” or “y”, then going in a third direction, “y” or “x”, is not significant. This is because as seen in Zhao figure 1 it is well-known, or blantly obvious, that one can extend the metal line in different x and y directions as one of ordinary skill in the art sees fit. Generally in the industry this is down by a layout engineer who job it is to make sure all elements can be routed efficiently based upon various specifications given to them. Thus, this claim is obvious to one of ordinary skill in the art before the effective filing date of the current application. PNG media_image1.png 318 631 media_image1.png Greyscale Regarding claim 22, wherein the second conductive layer is above the third conductive layer (this is considered a relabeling of the elements and, or routine skill in the art. For example, in order to route a line upward one may need to first run it downward and then back upward to avoid more important lines such as global clock lines, and the like. Therefore, this limitation would have been obvious to one of ordinary skill in the art.). Regarding claims 23-25, Claims 23-25 are directed to more wiring lines. These claims would have been obvious before the effective filing date for the same reasons as claims 1, and 21-22 above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT WALL whose telephone number is (571)272-9567. The examiner can normally be reached Monday to Thursday at 7:30am to 2:30pm PST. Interviews can be scheduled on Tuesday thru Thursday at 10am PST or 2pm PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINCENT WALL/ Primary Examiner, Art Unit 2898 Application/Control Number: 18/448,703 Page 2 Art Unit: 2898 Application/Control Number: 18/448,703 Page 3 Art Unit: 2898 Application/Control Number: 18/448,703 Page 4 Art Unit: 2898 Application/Control Number: 18/448,703 Page 5 Art Unit: 2898 Application/Control Number: 18/448,703 Page 6 Art Unit: 2898 Application/Control Number: 18/448,703 Page 7 Art Unit: 2898