Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 repeats the same limitation as the amended limitation in claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending U.S. Application No. 18/448746 (or Pub. No. US 2024/0105727 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claims 1 and 4, claims 1, 7 and 8 of Application No. 18/448746 disclose the limitations of the amended claim 1. Claim 7 of Application No. 18/448746 discloses “a third metal layer positioned below the lower source/drain regions and above the second metal layer, wherein the third metal layer includes at least one metal portion in contact with at least one of the lower source/drain regions”. Claim 8 discloses of Application No. 18/448746 discloses the amended limitation “a first via coupled between the at least one metal portion in the third metal layer and the power routing in the second metal layer”. Claim 1 of Application No. 18/448746 discloses the rest of the claimed limitations.
Regarding claim 2, claim 2 of Application No. 18/448746 discloses the claimed limitations.
Regarding claim 3, claims 6, 11, 13 and 16 of Application No. 18/448746 discloses the claimed limitations.
Regarding claim 5, claim 11 of Application No. 18/448746 discloses the claimed limitations.
Regarding claim 6, claim 7 of Application No. 18/448746 discloses the claimed limitations.
Regarding claim 7, claim 9 of Application No. 18/448746 discloses the claimed limitations.
Regarding claim 8, claim 10 of Application No. 18/448746 discloses the claimed limitations.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 1-8 are rejected under the double patenting rejection described above, but would be allowable if amended, or a timely filed terminal disclaimer may be used to overcome the obviousness-type double patenting rejection over the copending application.
Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-20 are allowed.
The following is an examiner's statement of reasons for allowance:
With respect to claim 9, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, wherein the second vertical transistor is a complementary transistor type to the first vertical transistor, the second gate being merged with the first gate; wherein the third metal layer includes: a first metal contact coupled to the lower source/drain region of the first vertical transistor; and a second metal contact coupled to the lower source/drain region of the second vertical transistor; a first via coupled between the first metal contact and the power routing in the second metal layer; and a second via coupled between the second metal contact and the power routing in the second metal layer. Claims 10-11 are included likewise as they depend from claim 9.
With respect to claim 12, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, further comprising: a first dielectric wall positioned on a first side of the first vertical transistor in the horizontal dimension; and a second dielectric wall positioned on a second side of the second vertical transistor in the horizontal dimension, the second side of the second vertical transistor being distal from the first side of the first vertical transistor in the apparatus.
With respect to claim 13, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, the fourth gate being merged with the third gate, wherein the fourth vertical transistor is parallel to the third vertical transistor with the at least some first spacing in the horizontal dimension between the third and fourth vertical transistors; wherein the second and fourth vertical transistors are a complementary transistor type to the first and third vertical transistors, and wherein the third and fourth vertical transistors are parallel to the first and second vertical transistors with at least some second spacing in the horizontal dimension, the second spacing being perpendicular to the first spacing; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes signal routing; a second metal layer located below the transistor region in the vertical dimension, wherein the second metal layer includes power routing; a third metal layer positioned below the lower source/drain regions and above the second metal layer, wherein the third metal layer includes: a first metal contact coupled to the lower source/drain region of the first vertical transistor; a second metal contact coupled to the lower source/drain region of the second vertical transistor; and a third metal contact coupled to the lower source/drain region of the third vertical transistor; a fourth metal layer positioned above the upper source/drain regions and below the first metal layer, wherein the fourth metal layer includes: a first metal strap coupled between the upper source/drain region of the first vertical transistor and the upper source/drain region of the third vertical transistor; and a second metal strap coupled between the upper source/drain region of the second vertical transistor and the upper source/drain region of the fourth vertical transistor; a first via coupled between the first metal contact and the power routing in the second metal layer; a second via coupled between the second metal contact and the power routing in the second metal layer; and a third via coupled between the third metal contact and the power routing in the second metal layer. Claims 14-16 are included likewise as they depend from claim 13.
With respect to claim 17, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claims, the fourth vertical transistor is parallel to the third vertical transistor with the at least some first spacing in the horizontal dimension between the third and fourth vertical transistors; wherein the second and fourth vertical transistors are a complementary transistor type to the first and third vertical transistors, and wherein the third and fourth vertical transistors are parallel to the first and second vertical transistors with at least some second spacing in the horizontal dimension, the second spacing being perpendicular to the first spacing; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes signal routing; a third metal layer positioned below the lower source/drain regions, wherein the third metal layer includes: a metal contact plate coupled to the lower source/drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor; a fourth metal layer positioned above the upper source/drain regions and below the first metal layer, wherein the fourth metal layer includes: a first metal strap coupled between the upper source/drain region of the first vertical transistor and the upper source/drain region of the second vertical transistor; and a second metal strap coupled between the upper source/drain region of the third vertical transistor and the upper source/drain region of the fourth vertical transistor. Claims 18-20 are included likewise as they depend from claim 17.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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March 7, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813