DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-20 in the reply filed on 05/20/26 is acknowledged. The traversal is on the ground(s) that the office fails to properly establish that examination of all pending claims would not present a serious burden.
Applicant’s election is acknowledged. Applicant’s traversal of the restriction is noted. Examiner notes that species A, B and C can be simultaneously examined. Examiner will examine claims 1-20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negate(left/right 302/304)d by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miao(USPGPUB DOCUMENT: 2019/0318963, hereinafter Miao) in view of Lee (USPGPUB DOCUMENT: 2017/0236823, hereinafter Lee).
Re claim 1 Miao discloses an apparatus, comprising: a first vertical transistor(left/right 104A/104B) formed in a transistor region of an integrated circuit cell structure, the first vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a first gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in a vertical dimension;a second vertical transistor(left/right 104A/104B) formed in the transistor region, the second vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a second gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the second vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along a first direction in a horizontal dimension with at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s;
Miao does not discloses a first metal layer() located above the transistor region in the vertical dimension, wherein the first metal layer includes parallel signal routing in the first direction;at least one gate(left/right 302/304) via coupled between the signal routing in the first metal layer and at least one of the first gate(left/right 302/304) and the second gate(left/right 302/304); anda second metal layer located below the transistor region in the vertical dimension,wherein the second metal layer includes parallel power routing in a second direction perpendicular to the first direction in the horizontal dimension.
Lee discloses a first metal layer(M11/M12/M13/M14 of Lee) located above the transistor region in the vertical dimension, wherein the first metal layer(M11/M12/M13/M14 of Lee) includes parallel signal routing[0042 of Lee] in the first direction; the signal routing[0042 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) and at least one of the first gate(left/right 302/304) and the second gate(left/right 302/304); anda second metal layer(M11/M12/M13/M14 of Lee) located below the transistor region[0043 of Lee] in the vertical dimension,wherein the second metal layer(M11/M12/M13/M14 of Lee) includes parallel power routing[0044,0045 of Lee] in a second direction perpendicular to the first direction in the horizontal dimension.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Miao in order to minimize the stress applied to the transistors may result in failed transistors that will lower process yield [0005, Miao]. In doing so, a first metal layer(M11/M12/M13/M14 of Lee) located above the transistor region in the vertical dimension, wherein the first metal layer(M11/M12/M13/M14 of Lee) includes parallel signal routing[0042 of Lee] in the first direction;at least one gate(left/right 302/304) via coupled between the signal routing[0042 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) and at least one of the first gate(left/right 302/304) and the second gate(left/right 302/304);
Re claim 2 Miao and Lee disclose the apparatus of claim 1, wherein the first vertical transistor(left/right 104A/104B) and the second vertical transistor(left/right 104A/104B) are complementary transistor types.
Re claim 3 Miao and Lee disclose the apparatus of claim 1, wherein the first vertical transistor(left/right 104A/104B) is a PMOS transistor, and wherein the second vertical transistor(left/right 104A/104B) is an NMOS transistor.
Re claim 4 Miao and Lee disclose the apparatus of claim 1, further comprising a gate(left/right 302/304) bridge that extends across the at least some spacing in the first direction between the vertical transistor(left/right 104A/104B)s, wherein the gate(left/right 302/304) bridge is coupled between the first gate(left/right 302/304) and the second gate(left/right 302/304).
Re claim 5 Miao and Lee disclose the apparatus of claim 4, wherein the at least one gate(left/right 302/304) via is coupled between the signal routing[0042 of Lee] in the first metal layer and a portion of the gate(left/right 302/304) bridge in the at least some spacing between the vertical transistor(left/right 104A/104B)s.
Re claim 6 Miao and Lee disclose the apparatus of claim 5, wherein the at least one gate(left/right 302/304) via is coupled between the gate(left/right 302/304) bridge and a signal input route of the signal routing[0042 of Lee] in the first metal layer.
Re claim 7 Miao and Lee disclose the apparatus of claim 1, further comprising a third metal layer positioned below the lower source/drain region(left/right 202A/202B)s and above the second metal layer, wherein the third metal layer includes at least one metal portion in contact with at least one of the lower source/drain region(left/right 202A/202B)s.
Re claim 8 Miao and Lee disclose the apparatus of claim 7, further comprising a lower via coupled between the at least one metal portion in the third metal layer and the power routing[0044,0045 of Lee] in the second metal layer.
Re claim 9 Miao and Lee disclose the apparatus of claim 1, further comprising:a fourth metal layer positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer, wherein the fourth metal layer includes at least one metal portion in contact with at least one of the upper source/drain region(left/right 1002A/1002B)s.
Re claim 10 Miao and Lee disclose the apparatus of claim 9, wherein the fourth metal layer includes:a first contact coupled to the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B), the first contact having a portion extending away from the upper source/drain region(left/right 1002A/1002B) in the second direction; anda second contact coupled to the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B), the second contact having a portion extending away from the upper source/drain region(left/right 1002A/1002B) in the second direction.
Re claim 11 Miao and Lee disclose the apparatus of claim 10, further comprising:a first contact via coupled between an end of the first contact distal from the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B) and a signal output route of the signal routing[0042 of Lee] in the first metal layer; anda second contact via coupled between an end of the second contact distal from the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B) and the signal output route.
Re claim 12 Miao and Lee disclose the apparatus of claim 9, further comprising:a third vertical transistor(left/right 104A/104B) formed in the transistor region, the third vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a third gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the third vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along the second direction;a fourth vertical transistor(left/right 104A/104B) formed in the transistor region, the fourth vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a fourth gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the fourth vertical transistor(left/right 104A/104B) is parallel to the third vertical transistor(left/right 104A/104B) along the first direction in the horizontal dimension with at least some spacing in the first direction between the third and fourth vertical transistor(left/right 104A/104B)s;a first contact in the fourth metal layer, wherein the first contact is coupled between the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B), the first contact having a portion extending beyond the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) in the second direction; anda second contact in the fourth metal layer, wherein the second contact is coupled between the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the fourth vertical transistor(left/right 104A/104B).
Re claim 13 Miao and Lee disclose the apparatus of claim 12, further comprising:a first contact via coupled between the portion of the first contact extending beyond the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) in the second direction and a signal output route of the signal routing[0042 of Lee] in the first metal layer;a metal extension portion coupled to a bottom of the lower source/drain region(left/right 202A/202B) of the fourth vertical transistor(left/right 104A/104B), wherein the metal extension portion extends towards a boundary of the integrated circuit cell from the bottom of the lower source/drain region(left/right 202A/202B) in the second direction; anda second contact via coupled between the metal extension portion and the signal output route.
Re claim 14 Miao and Lee disclose the apparatus of claim 9, wherein the fourth metal layer includes:a first contact coupled between the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B).
Re claim 15 Miao and Lee disclose the apparatus of claim 14, further comprising:a third vertical transistor(left/right 104A/104B) formed in the transistor region, the third vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a third gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the third vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along the second direction;a fourth vertical transistor(left/right 104A/104B) formed in the transistor region, the fourth vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a fourth gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the fourth vertical transistor(left/right 104A/104B) is parallel to the third vertical transistor(left/right 104A/104B) along the first direction in the horizontal dimension with at least some spacing in the first direction between the third and fourth vertical transistor(left/right 104A/104B)s; anda second contact in the fourth metal layer, wherein the second contact is coupled between the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the fourth vertical transistor(left/right 104A/104B).
Re claim 16 Miao and Lee disclose the apparatus of claim 15, further comprising a third contact coupled between the lower source/drain region(left/right 202A/202B)s of the first, second, third, and fourth vertical transistor(left/right 104A/104B)s, wherein the first gate(left/right 302/304), the second gate(left/right 302/304), the third gate(left/right 302/304), and the fourth gate(left/right 302/304) include, respectively, a first gate(left/right 302/304) extension, a second gate(left/right 302/304) extension, a third gate(left/right 302/304) extension, and a fourth gate(left/right 302/304) extension, wherein each gate(left/right 302/304) extension extends horizontally at least some distance in the second direction from its respective gate(left/right 302/304), the apparatus further comprising:a first gate(left/right 302/304) via coupled between the first gate(left/right 302/304) extension and a first signal input route of the signal routing[0042 of Lee] in the first metal layer, wherein the first gate(left/right 302/304) via is the at least one gate(left/right 302/304) via;a second gate(left/right 302/304) via coupled between the second gate(left/right 302/304) extension and the first signal input route of the signal routing[0042 of Lee] in the first metal layer;a third gate(left/right 302/304) via coupled between the third gate(left/right 302/304) extension and a second signal input route of the signal routing[0042 of Lee] in the first metal layer;a fourth gate(left/right 302/304) via coupled between the fourth gate(left/right 302/304) extension and the second signal input route of the signal routing[0042 of Lee] in the first metal layer; anda contact via coupled between the third contact and the first signal input route.
Re claim 17 Miao discloses an apparatus, comprising:a first vertical transistor(left/right 104A/104B) formed in a transistor region of an integrated circuit cell structure, the first vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a first gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in a vertical dimension;a second vertical transistor(left/right 104A/104B) formed in the transistor region, the second vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a second gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the second vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along a first direction in a horizontal dimension with at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s;
Miao does not discloses a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes parallel signal routing in the first direction;a first gate(left/right 302/304) bridge that extends across the at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s, wherein the first gate(left/right 302/304) bridge is coupled between the first gate(left/right 302/304) and the second gate(left/right 302/304); a first gate(left/right 302/304) via coupled between a first signal input route of the signal routing in the first metal layer and the first gate(left/right 302/304) bridge; a second metal layer located below the transistor region in the vertical dimension,wherein the second metal layer includes parallel power routing in a second direction perpendicular to the first direction in the horizontal dimension;a third metal layer positioned below the lower source/drain region(left/right 202A/202B)s and above the second metal layer, wherein the third metal layer includes lower metal contacts coupled to the lower source/drain region(left/right 202A/202B)s; lower contact vias between the lower metal contacts and the power routing in the second metal layer; a fourth metal layer positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer, wherein the fourth metal layer includes upper metal contacts coupled to the upper source/drain region(left/right 1002A/1002B)s, the upper metal contacts having portions extending away from the upper source/drain region(left/right 1002A/1002B)s in the second direction; and a first set of upper contact vias coupled between a first signal output route of the signal routing in the first metal layer and the upper metal contacts coupled to the first and second vertical transistor(left/right 104A/104B)s.
Lee discloses a first metal layer(M11/M12/M13/M14 of Lee) located above the transistor region in the vertical dimension, wherein the first metal layer(M11/M12/M13/M14 of Lee) includes parallel signal routing[0042,0044,0045 of Lee] in the first direction; a second metal layer(M11/M12/M13/M14 of Lee) located below the transistor region in the vertical dimension,wherein the second metal layer(M11/M12/M13/M14 of Lee) includes parallel power routing[0042,0044,0045 of Lee] in a second direction perpendicular to the first direction in the horizontal dimension; lower contact(CA1/CA2/CA3/CA4 of Lee) vias between the lower metal contact(CA1/CA2/CA3/CA4 of Lee)s and the power routing[0042,0044,0045 of Lee] in the second metal layer(M11/M12/M13/M14 of Lee); a fourth metal layer(M11/M12/M13/M14 of Lee) positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer(M11/M12/M13/M14 of Lee), wherein the fourth metal layer(M11/M12/M13/M14 of Lee) includes upper metal contact(CA1/CA2/CA3/CA4 of Lee)s coupled to the upper source/drain region(left/right 1002A/1002B)s,
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Miao in order to minimize the stress applied to the transistors may result in failed transistors that will lower process yield [0005, Miao]. In doing so, a first gate(left/right 302/304) bridge that extends across the at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s, wherein the first gate(left/right 302/304) bridge is coupled between the first gate(left/right 302/304) and the second gate(left/right 302/304); a first gate(left/right 302/304) via coupled between a first signal input route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) and the first gate(left/right 302/304) bridge; wherein the third metal layer(M11/M12/M13/M14 of Lee) includes lower metal contact(CA1/CA2/CA3/CA4 of Lee)s coupled to the lower source/drain region(left/right 202A/202B)s;; a fourth metal layer(M11/M12/M13/M14 of Lee) positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer(M11/M12/M13/M14 of Lee), wherein the fourth metal layer(M11/M12/M13/M14 of Lee) includes upper metal contact(CA1/CA2/CA3/CA4 of Lee)s coupled to the upper source/drain region(left/right 1002A/1002B)s, the upper metal contact(CA1/CA2/CA3/CA4 of Lee)s having portions extending away from the upper source/drain region(left/right 1002A/1002B)s in the second direction; and a first set of upper contact(CA1/CA2/CA3/CA4 of Lee) vias coupled between a first signal output route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) and the upper metal contact(CA1/CA2/CA3/CA4 of Lee)s coupled to the first and second vertical transistor(left/right 104A/104B)s.
Re claim 18 Miao and Lee disclose the apparatus of claim 17, wherein the lower contact vias include:a first set of lower contact vias coupled between a first power route of the power routing in the second metal layer and a lower metal contact coupled to the first vertical transistor(left/right 104A/104B); anda second set of lower contact vias coupled between a second power route of the power routing in the second metal layer and a lower metal contact coupled to the second vertical transistor(left/right 104A/104B).
Re claim 19 Miao discloses an apparatus, comprising:a first vertical transistor(left/right 104A/104B) formed in a transistor region of an integrated circuit cell structure, the first vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a first gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in a vertical dimension; a second vertical transistor(left/right 104A/104B) formed in the transistor region, the second vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a second gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the second vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along a first direction in a horizontal dimension with at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s; a third vertical transistor(left/right 104A/104B) formed in the transistor region, the third vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a third gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the third vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along a second direction perpendicular to the first direction in the horizontal dimension with at least some spacing in the second direction between the first and third vertical transistor(left/right 104A/104B)s; a fourth vertical transistor(left/right 104A/104B) formed in the transistor region, the fourth vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a fourth gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the fourth vertical transistor(left/right 104A/104B) is parallel to the third vertical transistor(left/right 104A/104B) along the first direction with at least some spacing in the first direction between the third and fourth vertical transistor(left/right 104A/104B)s, andwherein the fourth vertical transistor(left/right 104A/104B) is parallel to the second vertical transistor(left/right 104A/104B) along the second direction with at least some spacing in the second direction between the second and fourth vertical transistor(left/right 104A/104B)s;
Miao does not discloses anda first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes parallel signal routing in the first direction; a first gate(left/right 302/304) bridge that extends across the at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s, wherein the first gate(left/right 302/304) bridge is coupled between the first gate(left/right 302/304) and the second gate(left/right 302/304); a second gate(left/right 302/304) bridge that extends across the at least some spacing in the first direction between the third and fourth vertical transistor(left/right 104A/104B)s, wherein the second gate(left/right 302/304) bridge is coupled between the third gate(left/right 302/304) and the fourth gate(left/right 302/304);a first gate(left/right 302/304) via coupled between a first signal input route of the signal routing in the first metal layer and the first gate(left/right 302/304) bridge; a second gate(left/right 302/304) via coupled between a second signal input route of the signal routing in the first metal layer and the second gate(left/right 302/304) bridge; a second metal layer located below the transistor region in the vertical dimension,wherein the second metal layer includes parallel power routing in a second direction perpendicular to the first direction in the horizontal dimension;a third metal layer positioned below the lower source/drain region(left/right 202A/202B)s and above the second metal layer, wherein the third metal layer includes:a first lower metal contact coupled to the lower source/drain region(left/right 202A/202B) of the first vertical transistor(left/right 104A/104B);a second lower metal contact coupled to the lower source/drain region(left/right 202A/202B) of the second vertical transistor(left/right 104A/104B);a third lower metal contact coupled to the lower source/drain region(left/right 202A/202B) of the third vertical transistor(left/right 104A/104B); anda fourth lower metal contact coupled to the lower source/drain region(left/right 202A/202B) of the fourth vertical transistor(left/right 104A/104B), wherein the fourth lower metal contact includes a metal extension portion extends from the lower source/drain region(left/right 202A/202B) towards a boundary of the integrated circuit cell in the second direction;a fourth metal layer positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer, wherein the fourth metal layer includes:a first upper contact, wherein the first upper contact is coupled between the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B), the first upper contact having a portion extending beyond the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) in the second direction; anda second upper contact in the fourth metal layer, wherein the second upper contact is coupled between the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the fourth vertical transistor(left/right 104A/104B);a first contact via coupled between the portion of the first upper contact extending beyond the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) in the second direction and a signal output route of the signal routing in the first metal layer; and a second contact via coupled between the metal extension portion of the fourth lower metal contact and the signal output route.
Lee discloses anda first metal layer(M11/M12/M13/M14 of Lee) located above the transistor region in the vertical dimension, wherein the first metal layer(M11/M12/M13/M14 of Lee) includes parallel signal routing[0042,0044,0045 of Lee] in the first direction; a first lower metal contact(CA1/CA2/CA3/CA4 of Lee)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Miao in order to minimize the stress applied to the transistors may result in failed transistors that will lower process yield [0005, Miao]. In doing so, a first metal layer(M11/M12/M13/M14 of Lee) located above the transistor region in the vertical dimension, wherein the first metal layer(M11/M12/M13/M14 of Lee) includes parallel signal routing[0042,0044,0045 of Lee] in the first direction; a first gate(left/right 302/304) bridge that extends across the at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s, wherein the first gate(left/right 302/304) bridge is coupled between the first gate(left/right 302/304) and the second gate(left/right 302/304); a second gate(left/right 302/304) bridge that extends across the at least some spacing in the first direction between the third and fourth vertical transistor(left/right 104A/104B)s, wherein the second gate(left/right 302/304) bridge is coupled between the third gate(left/right 302/304) and the fourth gate(left/right 302/304);a first gate(left/right 302/304) via coupled between a first signal input route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) and the first gate(left/right 302/304) bridge; a second gate(left/right 302/304) via coupled between a second signal input route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) and the second gate(left/right 302/304) bridge; a second metal layer(M11/M12/M13/M14 of Lee) located below the transistor region in the vertical dimension,wherein the second metal layer(M11/M12/M13/M14 of Lee) includes parallel power routing[0042,0044,0045 of Lee] in a second direction perpendicular to the first direction in the horizontal dimension;a third metal layer(M11/M12/M13/M14 of Lee) positioned below the lower source/drain region(left/right 202A/202B)s and above the second metal layer(M11/M12/M13/M14 of Lee), wherein the third metal layer(M11/M12/M13/M14 of Lee) includes:a first lower metal contact(CA1/CA2/CA3/CA4 of Lee) coupled to the lower source/drain region(left/right 202A/202B) of the first vertical transistor(left/right 104A/104B);a second lower metal contact(CA1/CA2/CA3/CA4 of Lee) coupled to the lower source/drain region(left/right 202A/202B) of the second vertical transistor(left/right 104A/104B);a third lower metal contact(CA1/CA2/CA3/CA4 of Lee) coupled to the lower source/drain region(left/right 202A/202B) of the third vertical transistor(left/right 104A/104B); anda fourth lower metal contact(CA1/CA2/CA3/CA4 of Lee) coupled to the lower source/drain region(left/right 202A/202B) of the fourth vertical transistor(left/right 104A/104B), wherein the fourth lower metal contact(CA1/CA2/CA3/CA4 of Lee) includes a metal extension portion extends from the lower source/drain region(left/right 202A/202B) towards a boundary of the integrated circuit cell in the second direction;a fourth metal layer(M11/M12/M13/M14 of Lee) positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer(M11/M12/M13/M14 of Lee), wherein the fourth metal layer(M11/M12/M13/M14 of Lee) includes:a first upper contact(CA1/CA2/CA3/CA4 of Lee), wherein the first upper contact(CA1/CA2/CA3/CA4 of Lee) is coupled between the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B), the first upper contact(CA1/CA2/CA3/CA4 of Lee) having a portion extending beyond the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) in the second direction; anda second upper contact(CA1/CA2/CA3/CA4 of Lee) in the fourth metal layer(M11/M12/M13/M14 of Lee), wherein the second upper contact(CA1/CA2/CA3/CA4 of Lee) is coupled between the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the fourth vertical transistor(left/right 104A/104B);a first contact(CA1/CA2/CA3/CA4 of Lee) via coupled between the portion of the first upper contact(CA1/CA2/CA3/CA4 of Lee) extending beyond the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) in the second direction and a signal output route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee); and a second contact(CA1/CA2/CA3/CA4 of Lee) via coupled between the metal extension portion of the fourth lower metal contact and the signal output route.
Re claim 20 Miao discloses an apparatus, comprising:a first vertical transistor(left/right 104A/104B) formed in a transistor region of an integrated circuit cell structure, the first vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a first gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in a vertical dimension;a second vertical transistor(left/right 104A/104B) formed in the transistor region, the second vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a second gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the second vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along a first direction in a horizontal dimension with at least some spacing in the first direction between the first and second vertical transistor(left/right 104A/104B)s;a third vertical transistor(left/right 104A/104B) formed in the transistor region, the third vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a third gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the third vertical transistor(left/right 104A/104B) is parallel to the first vertical transistor(left/right 104A/104B) along a second direction perpendicular to the first direction in the horizontal dimension with at least some spacing in the second direction between the first and third vertical transistor(left/right 104A/104B)s;a fourth vertical transistor(left/right 104A/104B) formed in the transistor region, the fourth vertical transistor(left/right 104A/104B) having a lower source/drain region(left/right 202A/202B), a fourth gate(left/right 302/304), and an upper source/drain region(left/right 1002A/1002B) stacked in the vertical dimension, wherein the fourth vertical transistor(left/right 104A/104B) is parallel to the third vertical transistor(left/right 104A/104B) along the first direction with at least some spacing in the first direction between the third and fourth vertical transistor(left/right 104A/104B)s, andwherein the fourth vertical transistor(left/right 104A/104B) is parallel to the second vertical transistor(left/right 104A/104B) along the second direction with at least some spacing in the second direction between the second and fourth vertical transistor(left/right 104A/104B)s;
Miao does not discloses a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes parallel signal routing in the first direction; a second metal layer located below the transistor region in the vertical dimension,wherein the second metal layer includes parallel power routing in a second direction perpendicular to the first direction in the horizontal dimension;a third metal layer positioned below the lower source/drain region(left/right 202A/202B)s and above the second metal layer, wherein the third metal layer includes a lower metal contact coupled between the lower source/drain region(left/right 202A/202B)s of the first, second, third, and fourth vertical transistor(left/right 104A/104B)s; a fourth metal layer positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer, wherein the fourth metal layer includes:a first upper contact coupled between the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B); anda second upper contact coupled between the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the fourth vertical transistor(left/right 104A/104B);a first gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the first gate(left/right 302/304); a second gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the second gate(left/right 302/304); a third gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the third gate(left/right 302/304); a fourth gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the fourth gate(left/right 302/304); a first gate(left/right 302/304) via coupled between the first gate(left/right 302/304) extension and a first signal input route of the signal routing in the first metal layer; a second gate(left/right 302/304) via coupled between the second gate(left/right 302/304) extension and the first signal input route of the signal routing in the first metal layer; a third gate(left/right 302/304) via coupled between the third gate(left/right 302/304) extension and a second signal input route of the signal routing in the first metal layer;a fourth gate(left/right 302/304) via coupled between the fourth gate(left/right 302/304) extension and the second signal input route of the signal routing in the first metal layer; and a contact via coupled between the lower metal contact and the first signal input route.
Lee discloses a first metal layer(M11/M12/M13/M14 of Lee) located above the transistor region in the vertical dimension, wherein the first metal layer(M11/M12/M13/M14 of Lee) includes parallel signal routing[0042,0044,0045 of Lee] in the first direction; a first upper contact(CA1/CA2/CA3/CA4 of Lee)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lee to the teachings of Miao in order to minimize the stress applied to the transistors may result in failed transistors that will lower process yield [0005, Miao]. In doing so, a first metal layer(M11/M12/M13/M14 of Lee) located above the transistor region in the vertical dimension, wherein the first metal layer(M11/M12/M13/M14 of Lee) includes parallel signal routing[0042,0044,0045 of Lee] in the first direction; a second metal layer(M11/M12/M13/M14 of Lee) located below the transistor region in the vertical dimension,wherein the second metal layer(M11/M12/M13/M14 of Lee) includes parallel power routing[0042,0044,0045 of Lee] in a second direction perpendicular to the first direction in the horizontal dimension;a third metal layer(M11/M12/M13/M14 of Lee) positioned below the lower source/drain region(left/right 202A/202B)s and above the second metal layer(M11/M12/M13/M14 of Lee) , wherein the third metal layer(M11/M12/M13/M14 of Lee) includes a lower metal contact(CA1/CA2/CA3/CA4 of Lee) coupled between the lower source/drain region(left/right 202A/202B)s of the first, second, third, and fourth vertical transistor(left/right 104A/104B)s; a fourth metal layer(M11/M12/M13/M14 of Lee) positioned above the upper source/drain region(left/right 1002A/1002B)s and below the first metal layer(M11/M12/M13/M14 of Lee) , wherein the fourth metal layer(M11/M12/M13/M14 of Lee) includes:a first upper contact(CA1/CA2/CA3/CA4 of Lee) coupled between the upper source/drain region(left/right 1002A/1002B) of the first vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the second vertical transistor(left/right 104A/104B); anda second upper contact(CA1/CA2/CA3/CA4 of Lee) coupled between the upper source/drain region(left/right 1002A/1002B) of the third vertical transistor(left/right 104A/104B) and the upper source/drain region(left/right 1002A/1002B) of the fourth vertical transistor(left/right 104A/104B);a first gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the first gate(left/right 302/304); a second gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the second gate(left/right 302/304); a third gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the third gate(left/right 302/304); a fourth gate(left/right 302/304) extension that extends horizontally at least some distance in the second direction from the fourth gate(left/right 302/304); a first gate(left/right 302/304) via coupled between the first gate(left/right 302/304) extension and a first signal input route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) ; a second gate(left/right 302/304) via coupled between the second gate(left/right 302/304) extension and the first signal input route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) ; a third gate(left/right 302/304) via coupled between the third gate(left/right 302/304) extension and a second signal input route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) ;a fourth gate(left/right 302/304) via coupled between the fourth gate(left/right 302/304) extension and the second signal input route of the signal routing[0042,0044,0045 of Lee] in the first metal layer(M11/M12/M13/M14 of Lee) ; and a contact(CA1/CA2/CA3/CA4 of Lee) via coupled between the lower metal contact(CA1/CA2/CA3/CA4 of Lee) and the first signal input route.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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