Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 1/6/2026 is acknowledged.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20100181613 A1).
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CLAIM 1. Kim et al. teaches a memory, comprising:
a substrate 100;
a plurality of bit lines 122 located on the substrate (Figs. 1 & 2), the plurality of bit lines 122 being parallel to each other and extending in a first direction (Fig. 1 – “FIRST DIRECTION”),
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a plurality of active pillars 120b located on the bit lines 122, bottom ends of the active pillars being connected to the bit lines;
a plurality of word lines 132 parallel to each other and extending in a second direction (Fig. 1 – “SECOND DIRECTION”), the word lines 132 surrounding outer sidewalls of the active pillars and exposing top ends of the active pillars 120a, and the active pillars and the word lines 132 jointly constituting vertical memory transistors of the memory (Abstract, ¶s [0036-37], Figs. 1 & 2),; and
a plurality of capacitors 138 and a plurality of connecting pads(Pads are disclosed as optional but “not illustrated”, as capacitors 138 may be connected through pads or directly connected to the active pillar 120. ¶[0063]), each of the capacitors 138 being located on each of the active pillars 120, and each of the connecting pads being located between the active pillar 120 and the capacitor 138 for electrically connecting the active pillar 120 and the capacitor 138 (Figs. 1 & 2);
wherein the first direction and the second direction are perpendicular to each other (Fig. 1 – First and second directions are located in the same plane. (e.g. XY plane, x and y axis are perpendicular defining a plane. First and second directions may be thought of x and y axis. Both the prior art and Claims refer to the directions as first and second.), and the plurality of active pillars 120 are arranged in hexagonal array (As best understood, the hexagonal array describes staggard pillars. In the art it is understood Pillars may be aligned or staggered as circular areas may be packed “to provide the greatest density of active pillar structures, i.e., to maximize the degree to which the device can be integrated.” - ¶[0026]); in a projection on a plane perpendicular to a third direction (e.g. Fig. 1 – a third direction would be into or out of the figure, z-axis) , a center of each of the active pillars is offset from a central axis of the bit line 122 to which the active pillar is connected, and the centers of two adjacent ones of the active pillars on a same bit line are offset in opposite directions from the central axis of the bit line, wherein the third direction is perpendicular to the first direction and the second direction, and the central axis of the bit line extends along the first direction (See marked up Fig. 1 below with the features highlighted for explicit clarity. & ¶s[0024-26]1).
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CLAIM 5. Kim et al. teaches a memory of claim 1, further comprising:
contact layers (Note: This limitation does not provide any clear distinction, under BRI “contact layers” could be any part/interface of the structure at the location.) located one-to-one on the bit lines and electrically connected with the bit lines (Kim Figs. 1-2 – depicts 1T1C cells).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20100181613 A1).
CLAIM 3. Kim et al. teaches a memory of claim 1, comprising:
a memory cell constituted by one of the vertical memory transistors and the capacitor located on the vertical memory transistor, however is silent upon wherein a cell size of the memory cell is 4F².
Where the cell of Kim would be 4F² would however be an obvious expectation from the teaching in Kim et al. paragraphs 24-26.
Figs. 1-2 depict the 1T1C memory cell structure. In semiconductor technology, 4F² (four F-squared) refers to the most compact, theoretical minimum area for a single memory cell in planar Dynamic Random Access Memory (DRAM) architecture. It represents the ultimate limit of conventional 2D cell scaling, allowing for the highest possible density of bits on a die. F represents the smallest dimension that a lithography process can produce (e.g., the width of the narrowest wire or the minimum half-pitch of the memory array). 4F² (four F-squared) refers to the most compact, theoretical minimum area for a single memory cell in planar Dynamic Random Access Memory (DRAM) architecture. It represents the ultimate limit of conventional 2D cell scaling, allowing for the highest possible density of bits on a die. This is the recognized teaching of Kim et al. paragraphs 24-26, “to provide the greatest density of active pillar structures, i.e., to maximize the degree to which the device can be integrated.”
In view of Kim et al.’s teaching, it would be obvious to a PHOSITA at the time of the invention to optimize the pitch and angle to reach a optimized packing density for a 1T1C memory cell array to achieve 4F².
CLAIM 4. Kim et al. teaches a memory of claim 1, wherein,
the plurality of bit lines are arranged in parallel and spaced apart from each other at an equal interval; a distance between two adjacent ones of the bit lines is a bit line distance, and a distance between the center of one of the active pillars and the central axis of the bit line to which the active pillar is connected is an offset distance (Kim Figs. 1-2). Wherein the offset distance is 1/3 to 2/3 of the bit line distance, is recognized from the teaching of Kim et al. to be optimization of packing density, as pitch and angle are disclosed to be optimizable parameters to achieve maximum number and density of cells (Kim ¶24-26).
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the offset distances through routine experimentation and optimization to obtain optimal or desired device performance because the offset distances is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to changes in size, proportion, or shape unless they produce a new and unexpected result or solve a specific problem in a non-obvious way; nor is it to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.04-05.
Claim(s) 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20100181613 A1) in view of Lee et al. (US 20220139920 A1)
CLAIM 6. Kim et al. teaches a memory of claim 5, wherein, each of the connecting pads comprises a first connecting pad extending perpendicular to a third direction and a second connecting pad extending in the third direction, the first connecting pad covers a top of one of the active pillars, and the second connecting pad is in contact with the first connecting pad ;
and/or,
each of the contact layers comprises a horizontal portion extending perpendicular to the third direction and a vertical portion extending parallel to the third direction, the horizontal portion covers a top of one of the bit lines, wherein the third direction is perpendicular to the first direction and the second direction.
Kim et al. disclosing the option of the contact pads, but not depicting the features is therefore silent upon the capability of the contact pads and covering a part of the sidewall of the one of the active pillars and/or that the vertical portions extend along a sidewall of the one of the bit lines.
Contact pads having such shape were known and provided in anagous 1T1C memory cell transistors. Lee et al. demonstrates an analogous capacitor having the claimed contact pad portion over the top surface of a vertical pillar transistor and extending over a finite portion of the pillar side walls some finite amount.
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Element numbers 235 in figures 2C and 2d reproduced above direct the view to the contact pad portion of the capacitor having the claimed shape in the analogous device structure. It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the contact pad portion of Kim with the contact pad portion as taught by Lee, since simple substitution of one known element for another to obtain predictable results (e.g. increased contact surface area for improved electrical contact and/or bonding strength) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 7. Kim et al. in view of Lee et al. teaches a memory of claim 6, however may be silent upon wherein,
along the third direction, a ratio of a height of the second connecting pad to a height of a portion of the active pillar above the word line is 0.5-0.75.
The recited dimensional ranges for the ration would however be recognized as a optimizable parameter because in dense 4F² designs, the bit line and storage node capacitor contacts are extremely close to adjacent cells. A connecting pad that is too large (high ratio) increases the surface area between adjacent cells, which would naturally lead to high parasitic capacitance. Conversely, a ratio that is too low can increase resistance, as it is understood wire resistance is a function of cross sectional area. As such, such ratio is recognized as a optimizable parameter for reducing parasitic capacitance while simultaneously minimizing contact resistance.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the dimensional ratio through routine experimentation and optimization to obtain optimal or desired device performance because the dimensional ratio is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
CLAIM 8. Kim et al. in view of Lee et al. teaches a memory of claim 6, however may be silent upon wherein, along the third direction, a ratio of a height of the vertical portion to a height of the bit line is 0.6-0.9.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the dimensional ratio through routine experimentation and optimization to obtain optimal or desired device performance because the dimensional ratio is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
CLAIM 9. Kim et al. in view of Lee et al. teaches a memory of claim 5, wherein,
a material of the connecting pads and a material of the contact layers are same (Per Kim et al. a contact pad/layer may be parts of the same structures thus, be the same material.).
CLAIM 10. Kim et al. in view of Lee et al. teaches a memory of claim 5, wherein,
the material of the connecting pads and/or the material of the contact layers comprises metal silicide (Kim et al. ¶[0028] – contacts between transistor and bit line may be silicide.).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to select a silicide material for an electrical contact layer or pad, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
CLAIM 11. Kim et al. in view of Lee et al. teaches a memory of claim 5, wherein,
each of the connecting pads and/or each of the contact layers comprises a multi- layer structure, and materials of respective layers of the multi-layer structure are different (Pads are disclosed as optional but “not illustrated”, as capacitors 138 may be connected through pads or directly connected to the active pillar 120. ¶[0063]. Therefore, in the scenario where the contact pad is a distinct separable layer, said layer would be an additional layer in the contact region, there by being “multi layer” (e.g. S/D layer, contact pad layer, capacitor layer).),
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/10/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Kim et al. - [0024] The first and second active pillar structures 120a and 12b may have substantially the same or substantially similar shapes. Furthermore, the first and second active pillar structures 120a and 12b may have substantially the same or substantially similar sizes. For example, the first and second active pillar structures 120a and 12b may have circular cross-sectional shapes, and a diameter of the upper surfaces of the first pillar structures 120a may be substantially the same as or substantially similar to a diameter of the upper surfaces of the second active pillar structures 120b. Furthermore, each of the first and the second active pillar structures 120a and 120b may have a lower portion, and an upper portion that is narrower than its lower portion. That is, the first and the second active pillar structures 120a and 120b may each have a step between upper and lower portions thereof.
[0025] In any case, the rows of second pillar structures 120b are alternately disposed, in the first direction, with the rows of first pillar structures 120a. (Hence, the reference to odd and even rows of first and second pillar structures 120a and 120b, respectively). Likewise, the odd columns of second pillar structures 120b are alternately disposed, in the second direction, with the odd rows of first pillar structures 120a. (Hence, the reference to even and odd columns of first and second pillar structures 120a and 120b, respectively). Moreover, the columns of the second active pillar structures 120b are spaced from the columns of the first active pillar structures 120a by a second pitch (P2), i.e., a spacing in the second direction. That is, the group of second pillar structures 120b is offset in the second direction from the group of first active pillar structures 120a by an amount equal to the second pitch (P2). Accordingly, respective ones of the first and the second active pillar structures 120a and 120b are alternately disposed along each of a series of lines extending diagonally with respect to the first and second directions.
[0026] In this respect, as shown best in FIG. 1, a first line connecting one second active pillar structure 120b and a first active pillar structure 120a adjacent one another along one of the diagonals, and a second line connecting the same second active pillar structure 120b and a second active pillar structure 120b adjacent one another in one of the rows, subtend an acute angle (R) in a range of about 20 degrees to about 70 degrees. That is, the diagonals along which the first and second active pillars 120a and 120b are alternately disposed intersect the rows along which the active pillars 120a (or 120b) are disposed at the angle (R). In one example embodiment, the angle (R) is about 45 degrees to provide the greatest density of active pillar structures, i.e., to maximize the degree to which the device can be integrated.