Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/3/2026.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ramaswamy (US 20190006376 A1).
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CLAIM 1: Ramaswamy teaches a semiconductor structure, comprising:
a substrate 11 (Fig. 3. [0042]1 substate 11 is to be below the construct ruction 8 of figures 1 and 2 as shown in figure 3.]; and
a stack structure 8 arranged on the substrate (Ramaswamy Fig. 1 & 2 - discloses memory array 10 fabricated relative to a base substrate. The construction includes a stacked structure comprising vertically alternating tiers 12 and 14 of insulative material [12] and memory cells 19 [semiconductor material 14] .)
wherein the stack structure 8 comprises a plurality of storage areas spaced apart from each other in a first direction, and a plurality of isolation walls 13, each of the plurality of isolation walls being arranged between any two adjacent storage areas 19 of the plurality of storage areas (Figs. 2&3- Insulating material 13(analogous to isolation walls) located horizontally between memory cells 19 and extending elevationally through the stack (Figs. 1-3) These memory cells 19 comprise storage areas that are laterally spaced apart in a first direction (e.g. y-axis) by the insulating material 13.),
wherein each of the plurality of storage areas 19 comprises a plurality of memory cells spaced apart from each other in a second direction (Figs. 1 & 3, memory cells 19 arranged vertically in the z-axis direction and separated by insulating material 16 [layer 12].),
each of the plurality of memory cells 19 comprising a transistor structure 27 (e.g. gate 26, gate insulator 28, S/D 20/22), and a capacitor structure 34 arranged on a side surface of the transistor structure in a third direction (x-axis) and electrically connected to the transistor structure (As shown in figs. 1-3, the capacitor 34 is arranged on a sider surface of the transistor in a horizontal direction and is electrically connected to the S/D region 22 as it passes though the S/D layer region 22. See ¶[0043-44]2.),
an outline of a projection of the capacitor structure on a top surface of the substrate being in a shape of a rectangle or a rounded rectangle, wherein a width of the transistor structure is equal to a width of the capacitor structure in the first direction, and the transistor structure is aligned with the capacitor structure in the third direction (In Fig. 1, the transistor 25 (comprising gate 26 and source/drain regions 20/22) is aligned with the capacitor 34 in a horizontal direction (third direction), however Ramaswamy may be silent on explicitly stating they have “equal width”. It would have been obvious to a PHOSITA to make the width of the transistor structure equal to the width of the capacitor structure in the first direction . As the structures are formed by patterning the same transistor material tiers 14 and are laterally bounded by the same insulating material 13 (Fig. 1-3), maintaining a uniform width across both components simplifies the lithographic patterning and etching processes. Because the claim does not specify a precise measurement point for defining boundaries of “width” and the reference teaches forming these components within shared lateral boundaries, it would at least be obvious design choice to provide them with substantially equal widths for efficient use of the tier area and to ensure proper electrical coupling between the source/drain and the capacitor.), and
wherein each of the first direction and the third direction is parallel to the top surface of the substrate, the second direction is perpendicular to the top surface of the substrate, and the first direction intersects with the third direction (Ramaswamy describes the tiers as vertically alternating (second direction, perpendicular to the substrate 11). The current flow between source/drain regions 20/22 and the connection to the capacitor 34 is horizontal (third direction, parallel to the substrate). The sense lines 57 and access lines 27/63 are oriented in intersection horizontal direction parallel to the top surface of the substrate 11 (Fig. 1-3).
CLAIM 2: Ramaswamy teaches a semiconductor structure according to claim 1, wherein the stack structure further comprises: a plurality of isolation layers 12/13/16, wherein each of the plurality of isolation layers is arranged between any two adjacent memory cells 14/19 of the plurality of memory cells of a respective one of the plurality of storage areas, and each of the plurality of isolation layers is connected to a sidewall of a respective one of the plurality of isolation walls, wherein a thickness of each of the plurality of isolation layers ranges from 20 nm to 30 nm (Figs. 1-3 & ¶[0042] – Layers are discloses to be approximately 20nm [200 Ang.]. As understood from the cross sectional views of Fig. 2 & 13, insulator 13 on the side of layer 14/19, will have the same thickness as that of layer 14. ).
CLAIM 3: Ramaswamy teaches a semiconductor structure according to claim 1, further comprising a plurality of word lines 27, wherein each of the plurality of word lines is arranged in a respective one of the plurality of storage areas and extends in the second direction (Figs. 1-3 & ¶0002 & 46] - access line is synonymous with word line.), and the plurality of word lines are spaced apart from each other in the first direction (Figs. 1-3 & ¶0046]), wherein the transistor structure comprises: a gate layer 26; a channel layer 24, wherein the channel layer is arranged around a periphery of the gate layer, an outline of a projection of the channel layer on the top surface of the substrate is in a shape of a rectangle or a rounded rectangle, or wherein the gate layer is arranged around a periphery of the channel layer, an outline of a projection of the gate layer on the top surface of the substrate is in a shape of a rectangle or a rounded rectangle (Figs. 1-3 & ¶0046]), and wherein each of the plurality of word lines 27 is connected with gate layers 26 which are adjacent to each other in the second direction in the respective one of the plurality of storage areas (Figs. 1-3 & ¶0044-46]); and a source region and a drain region, wherein the source region 22 is arranged at an end of the channel layer in the third direction, and the drain region 20 is arranged at an opposite end of the channel layer in the third direction (Figs. 1-3 & ¶0046]).
CLAIM 4: Ramaswamy teaches a semiconductor structure according to claim 3, wherein in a direction parallel to the top surface of the substrate, a width of the gate layer is greater than or equal to a width of each of the plurality of word lines, and wherein the transistor structure further comprises a gate dielectric layer arranged between the gate layer and the channel layer(Figs. 1-3 & ¶0046]).
Ramaswamy may be silent upon wherein a thickness of the gate dielectric layer is greater than 10 nm. Gate insulator thickness is a recognized optimizable parameter, commonly optimized for maximizing drive current while preventing leakage breakdown.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the thickness through routine experimentation and optimization to obtain optimal or desired device performance because the thickness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 5: Ramaswamy teaches a semiconductor structure according to claim 1, wherein the capacitor structure 34 comprises: an upper electrode layer 48; a dielectric layer arranged around a periphery of the upper electrode layer 43; and a lower electrode layer 46 arranged around a periphery of the dielectric layer, wherein the lower electrode layer is electrically connected to the transistor structure 20, and an outline of a projection of the lower electrode layer on the top surface of the substrate is in a shape of a rectangle or a rounded rectangle (e.g. rounded rectangle may be a circle. Fig. 2 – Note: the mere change in shape (e.g. rectangle, rounded square, oval, circle, etc.. ) is considered a obvious design choice to a PHOSITA (MPEP 2144.04) in the absence of unexpected results and/or benefit. Simple change in shape, may simply optimized surface area of the capacitor, providing engineering of desired capacitance. As such, change in generic shape, would be considered an obvious variant by a PHOSITA.).
CLAIM 6: Ramaswamy teaches a semiconductor structure according to claim 3, wherein the capacitor structure 34 comprises: an upper electrode layer 48; a dielectric layer 43 arranged around a periphery of the upper electrode layer; and a lower electrode layer 46, wherein the lower electrode layer comprises a first conductive layer arranged around a periphery of the dielectric layer, and a second conductive layer arranged around a periphery of the first conductive layer, wherein the second conductive layer is electrically connected to the transistor structure, and an outline of a projection of the second conductive layer on the top surface of the substrate is in a shape of a rectangle or a rounded rectangle (e.g. rounded rectangle may be a circle. Fig. 2 – Note: the mere change in shape (e.g. rectangle, rounded square, oval, circle, etc.. ) is considered a obvious design choice to a PHOSITA (MPEP 2144.04) in the absence of unexpected results and/or benefit. Simple change in shape, may simply optimized surface area of the capacitor, providing engineering of desired capacitance. As such, change in generic shape, would be considered an obvious variant by a PHOSITA.).
CLAIM 7: Ramaswamy teaches a semiconductor structure according to claim 6, wherein the drain region in the transistor structure is integrally formed with the second conductive layer, and wherein a material of the first conductive layer is different from a material of the second conductive layer, and the material of the second conductive layer is a silicon material containing doped ions ( Fig. 1-3, 31-32 & ¶[0044-46] – The second conductive layer may be formed integrally or separably, and is a different material than the first conductive layer.)
CLAIM 8: Ramaswamy teaches a semiconductor structure according to claim 1, wherein the capacitor structure comprises: an upper electrode layer, wherein a projection of the upper electrode layer on the top surface of the substrate is in a long strip shape (Figs. 9/11), and the upper electrode layer extends in the third direction (Figs. 9/11); a dielectric layer 50a/50b, wherein the dielectric layer is arranged around a periphery of the upper electrode layer 48a/48b, and an outline of a projection of the dielectric layer on the top surface of the substrate is in a shape of a rectangle or a rounded rectangle; and a lower electrode layer arranged around a periphery of the dielectric layer, wherein the lower electrode layer is electrically connected to the transistor structure, and an outline of a projection of the lower electrode layer on the top surface of the substrate is in a shape of a rectangle or a rounded rectangle; or wherein the capacitor structure comprises: an upper electrode layer, wherein the upper electrode layer comprises a plurality of sub-upper electrode layers spaced apart from each other in the third direction (i.e. stacked tiers); a dielectric layer, wherein the dielectric layer comprises a plurality of sub-dielectric layers spaced apart from each other in the third direction, and each of the plurality of sub-dielectric layers is arranged around a periphery of a respective one of the plurality of sub-upper electrode layers; and a lower electrode layer, wherein the lower electrode layer extends in the third direction and continuously covers peripheries the plurality of sub-dielectric layers which are spaced apart from each other in the third direction, the lower electrode layer is electrically connected to the transistor structure, and an outline of a projection of the lower electrode layer on the top surface of the substrate is in a shape of a rectangle or a rounded rectangle (e.g. rounded rectangle may be a circle. Fig. 2 – Note: the mere change in shape (e.g. rectangle (fig. 9), rounded square, oval, circle, strip [figs. 9/11] etc.. ) is considered a obvious design choice to a PHOSITA (MPEP 2144.04) in the absence of unexpected results and/or benefit. Simple change in shape, may simply optimized surface area of the capacitor, providing engineering of desired capacitance. As such, change in generic shape, would be considered an obvious variant by a PHOSITA.).
CLAIM 9: Ramaswamy teaches a semiconductor structure according to claim 8, wherein the capacitor structure comprises: a common electrode layer arranged in a respective one of the plurality of storage areas, wherein the common electrode layer extends in the second direction, and is connected with upper electrode layers which are adjacent to each other in the second direction in the respective one of the plurality of storage areas, wherein in a direction parallel to the top surface of the substrate, a width of the common electrode layer is less than or equal to a width of the upper electrode layer (Figs. 1-3, 9-12)
CLAIM 10: Ramaswamy teaches a semiconductor structure according to claim 3, further comprising: a plurality of bit lines, wherein the plurality of bit lines are spaced apart from each other in the second direction, each of the plurality of bit lines 57 (¶[0002]) is electrically connected to transistor structures which are spaced apart from each other in the first direction, and a material of each of the plurality of bit lines is a silicon material containing doped ions (Figs. 1-3, 9-12 - ¶[0049]- Polysilicon requires doped ions when used as a conductor. Thus, bit lines 57 would be expected to contain doped ions when polysilicon is selected for the purpose.)
CLAIM 11: Ramaswamy teaches a semiconductor structure according to claim 10, wherein the source region 22 in each of the transistor structures is integrally formed with a respective one of the plurality of bit lines 57 (Figs. 1-3, 9-12 – As the claim is drawn to a structure, recited process does not provide a further non-obvious distinction, as to form integrally or separably is recognized as obvious by a PHOSITA at the time of the invention. See MPEP 2144.04).
Conclusion
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/9/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Ramaswamy - [0042] Construction 8 includes vertically-alternating tiers 12 and 14 of insulative material 16 (e.g., comprising, consisting essentially of, or consisting of silicon nitride and/or doped or undoped silicon dioxide of a thickness of 200 Angstroms to 1,000 Angstroms) and memory cells 19, respectively. Only four memory cell outlines 19 are shown in FIGS. 2 and 3 for clarity, although eight memory cells are visible in FIGS. 2 and 3 and four in FIG. 1. Only two z-axis columns of memory cells are shown in FIG. 1, and isolating insulative/insulating material is not shown to assist the reader and provide better clarity as to horizontal and vertical layout of certain operative components. In some embodiments, tiers 14 may be considered as transistor-material tiers 14. Memory-cell tiers 14 may be of the same or different thickness as that of insulative material tiers 12, with the same thickness being shown. Construction 8 is shown as having four vertically-alternating tiers 12 and 14 (FIG. 3), although fewer or likely many more (e.g., dozens, hundreds, etc.) may be formed. Accordingly, more tiers 12 and 14 may be below the depicted tiers and above base substrate 11 and/or more tiers 12 and 14 may be above the depicted tiers. Insulating material 13 (e.g., the other of silicon nitride or silicon dioxide where insulative material 16 is one of silicon nitride or silicon dioxide) is horizontally between memory cells 19 and extends elevationally through the depicted stack of materials.
2Ramaswamy - [0043] Memory cells 19 individually comprise a transistor 25 and a capacitor 34. Transistor 25 comprises a first source/drain region 20 and a second source/drain region 22 (e.g., conductively-doped semiconductor material such as polysilicon or semiconductively-doped semiconductor material such as polysilicon for each) having a channel region 24 there-between (e.g., doped semiconductor material, such as polysilicon, but not to be intrinsically conductive). In some embodiments (but not shown), a conductively-doped semiconductor region and/or or another semiconductive region (e.g., LDD and/or halo regions) may be between channel region 24 and one or both of source/drain regions 20 and 22.
[0044] A gate 26 (e.g., one or more of elemental metal, a mixture or alloy of two or more elementals, conductive metal compounds, and conductively-doped semiconductive materials) is operatively proximate channel region 24. Specifically, in the depicted example, a gate insulator material 28 (e.g., silicon dioxide, silicon nitride, hafnium oxide, other high k insulator material, and/or ferroelectric material) is between gate 26 and channel region 24. In one embodiment and as shown, channel region 24 comprises two channel-region segments “s” and “t” on opposite sides (e.g., y-direction sides) of the gate in a straight-line horizontal cross-section (e.g., the cross-section shown by FIG. 2). Alternately in another embodiment, the channel region may be on only one side (not shown in FIGS. 1-3) of gate 26 in a straight-line horizontal cross-section. Regardless, at least a portion of channel region 24 is horizontally-oriented for horizontal current flow in the portion between first source/drain region 20 and second source/drain region 22. In the depicted example embodiment, all of channel region 24 is horizontally-oriented for horizontal current flow there-through. Regardless, when suitable voltage is applied to gate 26, a conductive channel can form within channel region 24 proximate gate insulator material 28 such that current is capable of flowing between source/drain regions 20 and 22.