DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, Modification A1, and Modification B2 (encompassed by claims 1-8) in the reply filed on 26 January 2026 is acknowledged.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "122b" and "123a" have both been used to designate the same layer in FIG. 5, 6, and 7. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 8 objected to because of the following informalities: amended claim 8 is provided with the incorrect identifier, “(Original).” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation, “the protruding structure further includes a first heterojunction structure, a second heterojunction structure, ..., and an n-th heterojunction structure that are sequentially stacked in a direction away from the substrate, and n is greater than or equal to 2, wherein the first heterojunction structure includes a first channel layer and a first barrier layer, the second heterojunction structure includes a second channel layer and a second barrier layer, ..., and the n-th heterojunction structure includes an n-th channel layer and an n-th barrier layer, and component proportions of at least two of the first barrier layer, the second barrier layer, ..., or the n-th barrier layer are different,” in lines 4-13 of claim 1. The bounds of this limitation are unclear. More specifically, the meaning of the particular limitation, “, …,” is unclear. Additionally, if n is equal to 2, the limitation contains reference to “a first heterojunction structure, a second heterojunction structure, …, and a [second] heterojunction structure,” as well as, “the first barrier layer, the second barrier layer, …, or the [second] barrier layer.” The meets and bounds of the above quoted limitation of lines 4-13 of claim 1 are unclear, and for the purpose of this office action, the limitation is interpreted to have the following meaning: the protruding structure further includes a plurality of two or more heterojunction structures and a plurality of two or more barrier layers, wherein the plurality of two or more barrier layers includes a first barrier layer and a second barrier layer, and the plurality of two or more heterojunction structures includes a first heterojunction structure and a second heterojunction structure that are sequentially stacked in a direction away from the substrate, wherein the first heterojunction structure includes a first channel region and the first barrier layer and the second heterojunction structure includes a second channel region and the second barrier layer, and component proportions of at least two barrier layers of the plurality of two or more barrier layers are different.
Claims 2, 3, 4, and 6 recite the limitation, “the first barrier layer, the second barrier layer, ..., and the n-th barrier layer,” in lines 1-2 of each of claims 2, 3, 4 and line 2 of claim 6. The meets and bounds of this limitation are unclear for the reasons described in the above listed rejection of claim 1. For the purpose of this office action, the limitation is interpreted to have the following meaning: the plurality of two or more barrier layers.
Claim 5 recites the limitation "the number of barrier layers above a barrier layer with a highest proportion of Al” in lines 1-2 of the claim and the limitation “the number of barrier layers below the barrier layer with the highest proportion of Al” in lines 3-4 of the claim. There is insufficient antecedent basis for these limitations in the claim.
Claim 6 is further rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: the relationship between an unidentified element and the proportion of Al of a barrier layer which remains unchanged, gradually decreases or gradually increases. It is unclear what the proportion of Al of a barrier layer is to be compared to, with respect to remaining unchanged, gradually decreasing or gradually increasing. For the purpose of this office action, the proportion of Al of a barrier layer is compared to the proportion of Al of adjacent barrier layers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US PGPub 20220085200 A1; hereinafter referred to as “Yoshida”) in view of Nela et al. ("Multi-channel nanowire devices for efficient power conversion," pg. 1-24; hereinafter referred to as “Nela”).
Re claim 1: A semiconductor structure, comprising: a substrate (FIG. 14: el. 10; para. abstract, 37); an insulation layer on the substrate (FIG. 14: el. 11; para. 37, 53); a semiconductor structure protruding from the insulation layer, wherein the semiconductor structure comprises a source region (para. 38), a drain region (para. 38) and a channel region between the source region and the drain region (FIG. 14: el. 14a-14d; para. 35, 38), and further includes a plurality of two or more heterojunction structures (FIG. 14: el. 12a, 12b, 12c, 12d; para. 35) and a plurality of two or more barrier layers (FIG. 14: el. 16a, 16b, 16c, 16d; para. 35), wherein the plurality of two or more barrier layers includes a first barrier layer and a second barrier layer (FIG. 14: el. 16a, 16b; para. 35), and the plurality of two or more heterojunction structures includes a first heterojunction structure and a second heterojunction structure that are sequentially stacked in a direction away from the substrate (FIG. 14: el. 12a, 12b, 12c, 12d; para. 35), wherein the first heterojunction structure includes a first channel region and the first barrier layer (FIG. 14: el. 12a, 14a, 16a; para. 35) and the second heterojunction structure includes a second channel region and the second barrier layer (FIG. 14: el. 12b, 14b, 16b; para. 35), and component proportions of at least two barrier layers of the plurality of two or more barrier layers are different (para. 55: sent. 4; Table 1: sample C); and a source electrode (FIG. 14: el. 22; para. 36) on the source region, a drain electrode (FIG. 14: el. 24; para. 36) on the drain region and a gate structure (FIG. 14: el. 26; para. 82) on the channel region.
Yoshida is silent as to a protruding structure.
In a similar field of endeavor, Nela teaches a semiconductor structure, comprising: a substrate (FIG. 1a: el. substrate); a protruding structure (FIG. 1a; pg. 4: para. 1|protruding structure is the 3-dimensional multi-channel device), wherein the protruding structure comprises a source region (FIG. 1a: el. source), a drain region (FIG. 1a: el. drain) and a channel region between the source region and the drain region (FIG. 1a, 1b|multi-channel nanowires below gate electrode), and the protruding structure further includes a plurality of two or more heterojunction structures (FIG. 2b; pg. 5: para. 1|several heterojunctions formed between barrier layers and GaN channel layers) and a plurality of two or more barrier layers (FIG. 2b: el. Type II barrier, Type I barrier(s); pg. 5: para. 1), and component proportions of at least two barrier layers of the plurality of two or more barrier layers are different (FIG. 2C, 2D; pg. 5: para. 1|Type I and Type II barrier layers comprise AlGaN layers with differing proportions of dopant components and also differing thicknesses); and a source electrode on the source region, a drain electrode on the drain region and a gate structure on the channel region (Fig. 1a, 1b). Nela also teaches a benefit of the fin semiconductor structure is effective control of the channel region and of electric fields of the channel region, as well as enhancement mode operation (pg. 1: abstract; pg. 3: para. 2-4; pg. 11: para. 1; FIG. 1b).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Yoshida and Nela to enable using the protruding fin structure of Nela in the semiconductor structure of Yoshida, for the benefit of effective control of the channel region and electric fields of the channel region and the benefit of enhancement mode operation.
Re claim 2: The combination of Yoshida and Nela teaches the semiconductor structure according to claim 1, wherein materials of the plurality of two or more barrier layers include AlGaN (Yoshida - para. 37).
Re claim 4: The combination of Yoshida and Nela teaches the semiconductor structure according to claim 2, wherein proportions of Al in the plurality of two or more barrier layers first increase and then decrease layer by layer from bottom to top (Yoshida - para. 55: sent. 4; Table 1: sample C).
Re claim 5: The combination of Yoshida and Nela teaches adjusting the electron concentration of the 2-dimensional electron gas (2DEG) formed in heterojunctions to impact the current carrying capacity of individual 2DEG channels (Yoshida – para. 19, para. 40-52). The combination of Yoshida and Nela further teach adjusting the electron concentration of the channels by adjusting the proportion of Al in the barrier layers in conjunction with setting a thickness of the barrier layers (para. 40-52, 72). The proportion of Al in each barrier layer and the relationship between the proportion of Al of a barrier layer with respect to the proportion of Al of neighboring barrier layers is a result effective variable which works alongside the barrier layer thickness to control the carrier concentration of the 2DEG channels. In the absence of an indication that the claimed range produces unexpected results or has criticality, it would have been obvious at the time of the effective filling date of the claimed invention to adjust the proportion of Al of a barrier layer with respect to the proportion of Al of neighboring barrier layers, to achieve the claimed relation of a number of barrier layers above a barrier layer with a highest proportion of Al being greater than or equal to a number of barrier layers below the barrier layer with the highest proportion of Al, as a matter of routine optimization.
Claims 1-3, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (WO 2021229702 A1; hereinafter referred to as “Saito”; translation relied upon in the following rejection is US PGPub 20230352599 A1) in view of Nela.
Re claim 1 (second mapping): Saito teaches a semiconductor structure, comprising: a substrate (FIG. 24: el. 10; para. 43, para. 91); an insulation layer on the substrate (FIG. 24: el. 11; para. 52); a source region (FIG. 24: el. 13; para. 43), a drain region (FIG. 24: el. 14; para. 43) and a channel region between the source region and the drain region (FIG. 24: el. 15W; para. 82), and further includes a plurality of two or more heterojunction structures (FIG. 24: el. 15a, 15b, 15c, 15d; para. 83) and a plurality of two or more barrier layers (FIG. 24: el. 28a, 28b, 28c, 28d; para. 84-85), wherein the plurality of two or more barrier layers includes a first barrier layer and a second barrier layer (FIG. 24: el. 28a, 28b; para. 84-85), and the plurality of two or more heterojunction structures includes a first heterojunction structure and a second heterojunction structure that are sequentially stacked in a direction away from the substrate (FIG. 24: el. 15a, 15b; para. 83), wherein the first heterojunction structure includes a first channel region and the first barrier layer (FIG. 24: el. 15a, 27a, 28a; para. 84) and the second heterojunction structure includes a second channel region and the second barrier layer (FIG. 24: el. 15b, 27b, 28b; para. 84), and component proportions of at least two barrier layers of the plurality of two or more barrier layers are different (para. 88); and a source electrode (FIG. 22: el. 17; para. 43) on the source region, a drain electrode (FIG. 24: el. 18; para. 43) on the drain region and a gate structure (FIG. 22: el. 19; para. 43) on the channel region. Saito is silent as to a protruding structure.
In a similar field of endeavor, Nela teaches a semiconductor structure, comprising: a substrate (FIG. 1a: el. substrate); a protruding structure (FIG. 1a; pg. 4: para. 1|protruding structure is the 3-dimensional multi-channel device), wherein the protruding structure comprises a source region (FIG. 1a: el. source), a drain region (FIG. 1a: el. drain) and a channel region between the source region and the drain region (FIG. 1a, 1b|multi-channel nanowires are below gate electrode), and the protruding structure further includes a plurality of two or more heterojunction structures (FIG. 2b; pg. 5: para. 1|several heterojunctions formed between barrier layers and GaN channel layers) and a plurality of two or more barrier layers (FIG. 2b: el. Type II barrier, Type I barrier(s); pg. 5: para. 1), and component proportions of at least two barrier layers of the plurality of two or more barrier layers are different (FIG. 2C, 2D; pg. 5: para. 1|Type I and Type II barrier layers comprise AlGaN layers with differing proportions of dopant components and also differing thicknesses); and a source electrode on the source region, a drain electrode on the drain region and a gate structure on the channel region (Fig. 1a, 1b). Nela also teaches a benefit of the fin semiconductor structure is effective control of the channel region and of electric fields of the channel region, as well as enhancement mode operation (pg. 1: abstract; pg. 3: para. 2-4; pg. 11: para. 1; FIG. 1b).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Saito and Nela to enable using the protruding fin structure of Nela in the semiconductor structure of Saito, for the benefit of effective control of the channel region and electric fields of the channel region and the benefit of enhancement mode operation.
Re claim 2 (second mapping): The combination of Saito and Nela teaches the semiconductor structure according to claim 1, wherein materials of the plurality of two or more barrier layers include AlGaN (Saito - para. 84, 88).
Re claim 3: The combination of Saito and Nela teaches the semiconductor structure according to claim 2, wherein proportions of Al in the plurality of two or more barrier layers gradually decrease layer by layer from bottom to top (Saito - para. 88).
Re claim 6: The combination of Saito and Nela teaches the semiconductor structure according to claim 2, wherein a proportion of Al of at least one barrier layer of the plurality of two or more barrier layers remains unchanged, gradually decreases or gradually increases (Saito – para. 88 |proportion of Al in the barrier layers gradually decreases layer by layer).
Claims 7, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Nela as applied to claim 1 above, and further in view of Joglekar et al. (“Large Signal Linearity Enhancement of AlGaN/GaN High Electron Mobility Transistors by Device-Level Vt Engineering for Transconductance Compensation,” pg. 1-4; hereinafter referred to as “Joglekar”).
Re claim 7: The combination of Yoshida and Nela teaches the semiconductor structure according to claim 1. The combination of Yoshida and Nela fails to teach a plurality of protruding structures, the source electrode is on multiple source regions, the drain electrode is on multiple drain regions, and the gate structure is on multiple channel regions.
In a similar field of endeavor, Joglekar teaches a semiconductor structure, wherein there are a plurality of protruding structures (FIG. 5a; pg. 2: para. 2; pg. 1: last paragraph), the source electrode is on multiple source regions (FIG. 5a; pg. 2: para. 2), the drain electrode is on multiple drain regions (FIG. 5a; pg. 2: para. 2), and the gate structure is on multiple channel regions (FIG. 5a; pg. 2: para. 2).
Joglekar also teaches a benefit of multiple fins with a shared source, drain, and gate electrode is improved transistor linearity through device level transconductance compensation (pg. 1: para. 1-2).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Yoshida and Nela with the teachings of Joglekar to enable using the multiple protruding fins with shared electrodes of Joglekar in the semiconductor structure of the combination of Yoshida and Nela, for the benefit of transconductance compensation and improved device linearity.
Re claim 8: The combination of Yoshida, Nela, and Joglekar teaches the semiconductor structure according to claim 7, wherein at least two of the plurality of the protruding structures have different widths (Joglekar - FIG. 5a; pg. 2: para. 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art discloses semiconductor structures including heterojunctions and a plurality of fins.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898