DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot in view of the new ground of rejection necessitated by amendment. The prior drawing objection is withdrawn in view of amendments to the drawings. The prior §112 rejections are withdrawn in view of the amended claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US PGPub 20200251582 A1; hereinafter referred to as “Li”) in view of Yoshida et al. (US PGPub 20220085200 A1; hereinafter referred to as “Yoshida”).
Re claim 1: Li teaches a semiconductor structure, comprising: a substrate (FIG. 1B: el. 104; para. 17); an insulation layer (FIG. 1B: el. STI; para. 18) on the substrate; a protruding structure connected to the substrate and protruding through the insulation layer (FIG. 1B: el. 108; para. 17), wherein the protruding structure comprises a channel region (para. 17: second to last sentence) and further includes a heterojunction structure (para. 17: second to last sentence) including a channel layer and a barrier layer (para. 17: second to last, third to last, and fourth to last sentences| heterojunction formed of an AlGaN barrier layer on a GaN channel layer). Li fails to teach wherein the protruding structure comprises a source region, a drain region, and a channel region between the source region and the drain region, and the protruding structure further includes a plurality of heterojunction structures sequentially stacked in a direction away from the substrate, the plurality of heterojunction structures comprising a first heterojunction structure including a first channel layer and a first barrier layer, a second heterojunction structure including a second channel layer and a second barrier layer, and an n-th heterojunction structure including an n-th channel layer and an n-th barrier layer, wherein n is greater than or equal to 3, and component proportions of at least two of barrier layers of the plurality of heterojunction structures are different; and a source electrode on the source region, a drain electrode on the drain region and a gate structure on the channel region; wherein the barrier layers of the plurality of heterojunction structures include AlGaN; wherein proportions of Al in the barrier layers of the plurality of heterojunction structures first increase and then decrease layer by layer in the direction away from the substrate; and wherein a number of barrier layers above a barrier layer having a highest proportion of Al is greater than or equal to a number of barrier layers below the barrier layer having the highest proportion of Al.
In a similar field of endeavor Yoshida teaches a semiconductor structure, comprising: a substrate (FIG. 14: el. 10; para. abstract, 37); a stack structure on the substrate, wherein the stack structure comprises a source region (para. 38), a drain region (para. 38) and a channel region between the source region and the drain region (FIG. 14: el. 14a-14d; para. 35, 38), and further includes a plurality of heterojunction structures (FIG. 14: el. 12a, 12b, 12c, 12d; para. 35) sequentially stacked in a direction away from the substrate (FIG. 14), the plurality of heterojunction structures comprising a first heterojunction structure (FIG. 14: el. 12a, 14a, 16a; para. 35) including a first channel layer (FIG. 14: el. 14a) and a first barrier layer (FIG. 14: el. 16a), a second heterojunction structure (FIG. 14: el. 12b, 14b, 16b; para. 35) including a second channel layer (FIG. 14: el. 14b) and a second barrier layer (FIG. 14: el. 16b), and an n-th heterojunction structure (FIG. 14: el. 12d, 14d, 16d; para. 35) including an n-th channel layer (FIG. 14: el. 14d) and an n-th barrier layer (FIG. 14: el. 16d), wherein n is greater than or equal to 3 (FIG. 14|n is 3 or 4), and component proportions of at least two of barrier layers of the plurality of heterojunction structures are different (para. 55: sent. 4; Table 1: sample C); and a source electrode (FIG. 14: el. 22; para. 36) on the source region, a drain electrode (FIG. 14: el. 24; para. 36) on the drain region and a gate structure (FIG. 14: el. 26; para. 82) on the channel region; wherein the barrier layers of the plurality of heterojunction structures include AlGaN (para. 37); wherein proportions of Al in the barrier layers of the plurality of heterojunction structures first increase and then decrease layer by layer in the direction away from the substrate (para. 55: sent. 4; Table 1: sample C); and wherein a number of barrier layers above a barrier layer having a highest proportion of Al is greater than or equal to a number of barrier layers below the barrier layer having the highest proportion of Al (barrier layer 16c has the highest proportion of Al; barrier layer 16d is above barrier layer 16c and thus a number of barrier layers above 16c can be 1; barrier layer 16b is below barrier layer 16c and thus a number of barrier layers below 16c can be 1; thus allowing for the “equal to” clause of this limitation to be met). Yoshida also teaches a benefit of an AlGaN/GaN high-electron mobility semiconductor device with multiple channels is increased drain current and power density along with ability to tailor characteristics of individual channels to improve performance and thermal efficiency of the device (para. 81, 19).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Li and Yoshida, to enable using the high-electron mobility channel stack of Yoshida in the high-electron mobility semiconductor fin device of Li, for the benefit of increased drain current and power density along with ability to tailor characteristics of individual channels to improve performance and thermal efficiency of the device.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Yoshida as applied to claim 1 above, and further in view of Joglekar et al. (“Large Signal Linearity Enhancement of AlGaN/GaN High Electron Mobility Transistors by Device-Level Vt Engineering for Transconductance Compensation,” pg. 1-4; hereinafter referred to as “Joglekar”).
Re claim 7: The combination of Li and Yoshida teaches the semiconductor structure according to claim 1. The combination of Li and Yoshida fails to teach a plurality of protruding structures, the source electrode is on multiple source regions, the drain electrode is on multiple drain regions, and the gate structure is on multiple channel regions.
In a similar field of endeavor, Joglekar teaches a semiconductor structure, wherein there are a plurality of protruding structures (FIG. 5a; pg. 2: para. 2; pg. 1: last paragraph), the source electrode is on multiple source regions (FIG. 5a; pg. 2: para. 2), the drain electrode is on multiple drain regions (FIG. 5a; pg. 2: para. 2), and the gate structure is on multiple channel regions (FIG. 5a; pg. 2: para. 2).
Joglekar also teaches a benefit of multiple fins with a shared source, drain, and gate electrode is improved transistor linearity through device level transconductance compensation (pg. 1: para. 1-2).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of the combination of Li and Yoshida with the teachings of Joglekar to enable using the multiple protruding fins with shared electrodes of Joglekar in the semiconductor structure of the combination of Li and Yoshida, for the benefit of transconductance compensation and improved device linearity.
Re claim 8: The combination of Li, Yoshida, and Joglekar teaches the semiconductor structure according to claim 7, wherein at least two of the plurality of protruding structures have different widths (Joglekar - FIG. 5a; pg. 2: para. 2).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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