DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 11/03/2025. Claims 1-20 are pending for this examination.
Oath/Declaration
The oath or declaration filed on 08/14/2023 is acceptable.
Election/Restrictions
Applicant’s election, without traverse, of species I: claims 1-8 and 16-20, in the “Response to Election / Restriction Filed” filed on 11/03/2025 is acknowledged and entered by Examiner. This office action considers claims 1-20 are thus pending for prosecution, of which, non-elected claims 9-15 are withdrawn, and elected claims 1-8 and 16-20 are examined on their merits.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 2013/0105963 A1; hereafter Choi) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer).
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Regarding claim 1. Choi discloses a flip-chip (Fig. [14], Para [ 0047-0050]) assembly, comprising:
a substrate (Fig. [14], substrate 144, Para [ 0054]); and
a semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]) attached and electrically connected to the substrate (Fig. [14], substrate 144) with a plurality of conductive bumps ( stack bump pads [132/134], Para [ 0052]), a middle portion of the semiconductor chip having a first thickness (Fig. [14], semiconductor die 124, Para [ 0061]), a corner portion of the semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]) having a smaller second thickness (Fig. [14], semiconductor die 124, Para [ 0061]), wherein the plurality of conductive bumps ( stack bump pads [132/134], Para [ 0052]) includes a first set of bumps ( stack bump pads [132/134], Para [ 0052]) vertically between the middle portion of the semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]) and the substrate (Fig. [14], substrate 144, Para [ 0054]), and a second set of bumps ( another stack bump pads [132/134], Para [ 0052]) vertically between the corner portion of the semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]) and the substrate (Fig. [14], substrate 144, Para [ 0054]).
But Choi does not disclose explicitly the semiconductor chip including at least one low-k dielectric layer adjacent to a device layer and to a metal interconnect layer thereof.
In a similar field of endeavor, Meyer discloses the semiconductor chip (Fig [4], semiconductor device 400, Para [ 0056]) including at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to a device layer (chip layer 402) and to a metal interconnect layer thereof (pad 412/ bump 408).
Since Choi and Meyer are both from the similar field of endeavor, and Meyer discloses configuration of semiconductor device. Therefore, the purpose disclosed by Meyer would have been recognized in the pertinent art of Choi. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi in light of Meyer teaching “the semiconductor chip (Fig [4], semiconductor device 400, Para [ 0056]) including at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to a device layer (chip layer 402) and to a metal interconnect layer thereof (pad 412/ bump 408)” for further advantage such as reliable semiconductor device integration.
Regarding claim 6. Choi and Meyer disclose the flip-chip assembly of claim 1, Choi further disclose wherein the semiconductor chip has a rectangular shape that includes four instances of the corner portion (Fig. [14], semiconductor die 124, Para [ 0061]).
Regarding claim 16. Choi discloses a semiconductor chip, comprising:
wherein a middle portion of the semiconductor chip has a first thickness (Fig. [14], semiconductor die 124, Para [ 0061]), and
a corner portion of the semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]) has a smaller second thickness (Fig. [14], semiconductor die 124, Para [ 0061]).
But Choi does not disclose explicitly a device layer; a metal interconnect layer; and at least one low-k dielectric layer adjacent to the device layer and to the metal interconnect layer.
In a similar field of endeavor, Meyer discloses a device layer (Fig [4], chip layer 402); a metal interconnect layer (pad 412/ bump 408); and at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to the device layer (Fig [4], chip layer 402) and to the metal interconnect layer (pad 412/ bump 408).
Since Choi and Meyer are both from the similar field of endeavor, and Meyer discloses configuration of semiconductor device. Therefore, the purpose disclosed by Meyer would have been recognized in the pertinent art of Choi. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi in light of Meyer teaching “a device layer (Fig [4], chip layer 402); a metal interconnect layer (pad 412/ bump 408); and at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to the device layer (Fig [4], chip layer 402) and to the metal interconnect layer (pad 412/ bump 408)” for further advantage such as reliable semiconductor device integration.
Regarding claim 17. Choi and Meyer disclose the semiconductor chip of claim 16, Choi further disclose further comprising:
a first set of conductive bumps (Fig. [14], bump pads [134], Para [ 0052]) formed on a first set of bonding pads (Fig. [14], bump pads [132], Para [ 0052]) of the semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]) and disposed vertically proximate to the middle portion of the semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]); and a second set of conductive bumps (Fig. [14], another bump pads [134], Para [ 0052]) formed on a second set of bonding pads (Fig. [14], another bump pads [132], Para [ 0052]) and disposed vertically proximate to the corner portion of the semiconductor chip (Fig. [14], semiconductor die 124, Para [ 0061]).
Claims 2-4 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 2013/0105963 A1; hereafter Choi) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of YU et al (US 2015/0364376 A1; hereafter YU).
Regarding claim 2. Choi and Meyer disclose the flip-chip assembly of claim 1, But Choi and Meyer do not disclose explicitly wherein the corner portion of the semiconductor chip has a varying thickness that gradually changes from the first thickness at an inner perimeter of the corner portion to the smaller second thickness at an edge of the semiconductor chip.
In a similar field of endeavor, YU discloses wherein the corner portion of the semiconductor chip has a varying thickness (Fig [7], semiconductor device 10c includes notch 134c, with varying thickness Para [0041]) that gradually changes from the first thickness at an inner perimeter of the corner portion to the smaller second thickness at an edge of the semiconductor chip (Fig [7], semiconductor device 10c includes notch 134c, Para [0041]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of YU teaching “wherein the corner portion of the semiconductor chip has a varying thickness (Fig [7], semiconductor device 10c includes notch 134c, with varying thickness Para [0041]) that gradually changes from the first thickness at an inner perimeter of the corner portion to the smaller second thickness at an edge of the semiconductor chip (Fig [7], semiconductor device 10c includes notch 134c, Para [0041])” for further advantage such as to improve singulation process to manufacture high functions and complicated structures while the size of the semiconductor devices is minimized.
Regarding claim 3. Choi and Meyer disclose the flip-chip assembly of claim 1, But Choi and Meyer do not disclose explicitly wherein the corner portion of the semiconductor chip has a constant thickness, the constant thickness being the smaller second thickness; and wherein the semiconductor chip has a step-like thickness change at an inner perimeter of the corner portion from the smaller second thickness to the first thickness.
In a similar field of endeavor, YU discloses wherein the corner portion of the semiconductor chip has a constant thickness (Fig [5], semiconductor device 10c includes notch 134, Para [0038]), the constant thickness being the smaller second thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038]); and wherein the semiconductor chip has a step-like thickness change at an inner perimeter of the corner portion from the smaller second thickness to the first thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of YU teaching “wherein the corner portion of the semiconductor chip has a constant thickness (Fig [5], semiconductor device 10c includes notch 134, Para [0038]), the constant thickness being the smaller second thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038]); and wherein the semiconductor chip has a step-like thickness change at an inner perimeter of the corner portion from the smaller second thickness to the first thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038])” for further advantage such as to improve singulation process to manufacture high functions and complicated structures while the size of the semiconductor devices is minimized.
Regarding claim 4. Choi and Meyer disclose the flip-chip assembly of claim 1, But Choi and Meyer do not disclose explicitly wherein an inner perimeter of the corner portion has a shape of a circular or elliptical arc.
In a similar field of endeavor, YU discloses wherein an inner perimeter of the corner portion has a shape of a circular or elliptical arc (Fig [8], semiconductor device 10d, Para [0038]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of YU teaching “wherein an inner perimeter of the corner portion has a shape of a circular or elliptical arc (Fig [8], semiconductor device 10d, Para [0038])” for further advantage such as to improve singulation process to manufacture high functions and complicated structures while the size of the semiconductor devices is minimized.
Regarding claim 19. Choi and Meyer disclose the semiconductor chip of claim 16, But Choi and Meyer do not disclose explicitly wherein the corner portion of the semiconductor chip has a varying thickness that gradually changes from the first thickness at an inner perimeter of the corner portion to the smaller second thickness at an edge of the semiconductor chip.
In a similar field of endeavor, YU discloses wherein the corner portion of the semiconductor chip has a varying thickness (Fig [7], semiconductor device 10c includes notch 134c, with varying thickness Para [0041]) that gradually changes from the first thickness at an inner perimeter of the corner portion to the smaller second thickness at an edge of the semiconductor chip (Fig [7], semiconductor device 10c includes notch 134c, Para [0041]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of YU teaching “wherein the corner portion of the semiconductor chip has a varying thickness (Fig [7], semiconductor device 10c includes notch 134c, with varying thickness Para [0041]) that gradually changes from the first thickness at an inner perimeter of the corner portion to the smaller second thickness at an edge of the semiconductor chip (Fig [7], semiconductor device 10c includes notch 134c, Para [0041])” for further advantage such as to improve singulation process to manufacture high functions and complicated structures while the size of the semiconductor devices is minimized.
Regarding claim 20. Choi and Meyer disclose the semiconductor chip of claim 16, But Choi and Meyer do not disclose explicitly wherein the corner portion of the semiconductor chip has a constant thickness, the constant thickness being the smaller second thickness, and the semiconductor chip has a step-like thickness change at an inner perimeter of the corner portion from the smaller second thickness to the first thickness.
In a similar field of endeavor, YU discloses wherein the corner portion of the semiconductor chip has a constant thickness (Fig [5], semiconductor device 10c includes notch 134, Para [0038]), the constant thickness being the smaller second thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038]); and wherein the semiconductor chip has a step-like thickness change at an inner perimeter of the corner portion from the smaller second thickness to the first thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of YU teaching “wherein the corner portion of the semiconductor chip has a constant thickness (Fig [5], semiconductor device 10c includes notch 134, Para [0038]), the constant thickness being the smaller second thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038]); and wherein the semiconductor chip has a step-like thickness change at an inner perimeter of the corner portion from the smaller second thickness to the first thickness Fig [5], semiconductor device 10c includes notch 134, Para [0038])” for further advantage such as to improve singulation process to manufacture high functions and complicated structures while the size of the semiconductor devices is minimized.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 2013/0105963 A1; hereafter Choi) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of Malatkar et al (US 2017/0186705 A1; hereafter Malatkar).
Regarding claim 5. Choi and Meyer disclose the flip-chip assembly of claim 1, But Choi and Meyer do not disclose explicitly wherein a footprint of the corner portion on a main surface of the semiconductor chip has a polygonal shape.
In a similar field of endeavor, Malatkar discloses wherein a footprint of the corner portion on a main surface of the semiconductor chip has a polygonal shape (Fig [1], semiconductor device 10d, Para [0034-0038, 0065-0066]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of Malatkar teaching “wherein an inner perimeter of the corner portion has a shape of a circular or elliptical arc (Fig [8], semiconductor device 10d, Para [0038])” for further advantage such as improved I/O routing, improved reliability, and lower warpage during mounting of electronic components.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 2013/0105963 A1; hereafter Choi) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of Eom et al (US 2011/0089577 A1; hereafter Eom).
Regarding claim 7. Choi and Meyer disclose the flip-chip assembly of claim 1, But Choi and Meyer do not disclose explicitly wherein a bump of the plurality of conductive bumps comprises:
a cylindrical stub directly attached to the semiconductor chip;
a reflowed solder cap directly attached to the substrate; and a barrier layer sandwiched between the cylindrical stub and the reflowed solder cap.
In a similar field of endeavor, Eom discloses wherein a bump of the plurality of conductive bumps comprises:
a cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) directly attached to the semiconductor chip (Fig 1, substrate 30);
a reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032]) directly attached to the substrate (Fig 1, substrate 30, Para [ 0030-0032]); and a barrier layer (solder 14, Para [ 0030-0032]) sandwiched between the cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) and the reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of Eom teaching “a cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) directly attached to the semiconductor chip (Fig 1, substrate 30); a reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032]) directly attached to the substrate (Fig 1, substrate 30, Para [ 0030-0032]); and a barrier layer (solder 14, Para [ 0030-0032]) sandwiched between the cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) and the reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032])” for further advantage such as bonding a flip chip while increasing the manufacturing yield.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 2013/0105963 A1; hereafter Choi) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of IWAI et al (US 2021/0066238 A1; hereafter IWAI).
Regarding claim 8. Choi and Meyer disclose the flip-chip assembly of claim 1, But Choi and Meyer do not disclose explicitly wherein a difference between the first thickness and the smaller second thickness is in a range between 0.02 mm and 0.2 mm.
In a similar field of endeavor, IWAI discloses wherein a difference between the first thickness and the smaller second thickness is in a range between 0.02 mm and 0.2 mm (Fig [9], semiconductor device 10, Para [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of IWAI teaching “wherein a difference between the first thickness and the smaller second thickness is in a range between 0.02 mm and 0.2 mm (Fig [9], semiconductor device 10, Para [0069-0070])” for further advantage such as improved I/O routing, improved reliability, and lower warpage during mounting of electronic components.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (US 2013/0105963 A1; hereafter Choi) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of KIM (US 2023/0178468 A1; hereafter KIM).
Regarding claim 18. Choi and Meyer disclose the semiconductor chip of claim 17, But Choi and Meyer do not disclose explicitly wherein the conductive bumps comprise copper pillars.
In a similar field of endeavor, KIM discloses wherein the conductive bumps comprise copper pillars (Fig [2], Para [0029]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of KIM teaching “wherein the conductive bumps comprise copper pillars (Fig [2], Para [0029])” for further advantage such to provide reliable electrical connection by using well known process.
Conclusion
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898