DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 05/13/2026. Claims 1-8 and 16-22 are pending for this examination.
Claim Objections
Claim 18 is objected to because of the following informalities:
Claim 18 depends on cancelled claim 17. It appears claim 18 should be depend on claim 16. Appropriate correction is required.
Response to Arguments
Applicant’s reply filed on 05/13/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al (US 2022/0406752 A1; hereafter WANG) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer).
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Regarding claim 1. WANG discloses a flip-chip (Fig. [6], semiconductor die 100-1, Para [ 0041-0067]) assembly, comprising:
a substrate (Fig. [6], interposer substrate 120, Para [ 0035]); and
a semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064]) attached and electrically connected to the substrate (Fig. [6], interposer substrate 120, Para [ 0035]) with a plurality of conductive bumps ( stack bump pads [105/103], Para [ 0031]), a middle portion of the semiconductor chip having a first thickness (Fig. [6], semiconductor die 100-1, Para [ 0064]), a corner portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a) having a smaller second thickness (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a), wherein the plurality of conductive bumps ( stack bump pads [105/103], Para [ 0031]) includes a first set of bumps ( stack bump pads [105/103], Para [ 0031]) vertically between the middle portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064]) and the substrate (Fig. [6], interposer substrate 120, Para [ 0035]) , and a second set of bumps ( another stack bump pads [105/103], Para [ 0031]) vertically between the corner portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a) and the substrate (Fig. [6], interposer substrate 120, Para [ 0035]) , the second set including one or more bumps ( another stack bump pads [105/103], Para [ 0031]) for which a vertical projection onto the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a) is fully between an inner perimeter of the corner portion and an edge of the corner portion (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
But WANG does not disclose explicitly the semiconductor chip including at least one low-k dielectric layer adjacent to a device layer and to a metal interconnect layer thereof.
In a similar field of endeavor, Meyer discloses the semiconductor chip (Fig [4], semiconductor device 400, Para [ 0056]) including at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to a device layer (chip layer 402) and to a metal interconnect layer thereof (pad 412/ bump 408).
Since WANG and Meyer are both from the similar field of endeavor, and Meyer discloses configuration of semiconductor device. Therefore, the purpose disclosed by Meyer would have been recognized in the pertinent art of WANG. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG in light of Meyer teaching “the semiconductor chip (Fig [4], semiconductor device 400, Para [ 0056]) including at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to a device layer (chip layer 402) and to a metal interconnect layer thereof (pad 412/ bump 408)” for further advantage such as reliable semiconductor device integration.
Regarding claim 2. WANG and Meyer disclose the flip-chip assembly of claim 1, WANG further disclose wherein the corner portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a) has a varying thickness that gradually changes from the first thickness at the inner perimeter of the corner portion to the smaller second thickness at the edge of the corner portion (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
Regarding claim 3. WANG and Meyer disclose the flip-chip assembly of claim 1, WANG further disclose wherein the corner portion of the semiconductor chip has a constant thickness (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a), the constant thickness being the smaller second thickness (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a); and wherein the semiconductor chip has a step-like thickness change at the inner perimeter of the corner portion from the smaller second thickness to the first thickness (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
Regarding claim 4. WANG and Meyer disclose the flip-chip assembly of claim 1, WANG further disclose wherein the inner perimeter of the corner portion has a shape of a circular or elliptical arc (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
Regarding claim 6. WANG and Meyer disclose the flip-chip assembly of claim 1, WANG further disclose wherein the semiconductor chip has a rectangular shape that includes four instances of the corner portion (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
Regarding claim 16. WANG discloses a semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064]), comprising:
a first set of conductive bumps (pads [103], Para [ 0031]) formed on a first set of bonding pads (bumps [105], Para [ 0031]) of the semiconductor chip (semiconductor die 100-1, Para [ 0064]) and disposed vertically proximate to a middle portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064]); and
a second set of conductive bumps (pads [103], Para [ 0031]) formed on a second set of bonding pads (bumps [105], Para [ 0031]) and disposed vertically proximate to a corner portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a), wherein the middle portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064]) has a first thickness, and the corner portion of the semiconductor chip has a smaller second thickness (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a); and
wherein the second set of conductive bumps (pads [103], Para [ 0031]) includes one or more bumps (pads [103], Para [ 0031]) for which a vertical projection onto the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064]) is fully between an inner perimeter of the corner portion and an edge of the corner portion (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
But Choi does not disclose explicitly a device layer; a metal interconnect layer; and at least one low-k dielectric layer adjacent to the device layer and to the metal interconnect layer.
In a similar field of endeavor, Meyer discloses a device layer (Fig [4], chip layer 402); a metal interconnect layer (pad 412/ bump 408); and at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to the device layer (Fig [4], chip layer 402) and to the metal interconnect layer (pad 412/ bump 408).
Since WANG and Meyer are both from the similar field of endeavor, and Meyer discloses configuration of semiconductor device. Therefore, the purpose disclosed by Meyer would have been recognized in the pertinent art of Choi. Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG in light of Meyer teaching “a device layer (Fig [4], chip layer 402); a metal interconnect layer (pad 412/ bump 408); and at least one low-k dielectric layer (low-k dielectric layer 404, Para [ 0056]) adjacent to the device layer (Fig [4], chip layer 402) and to the metal interconnect layer (pad 412/ bump 408)” for further advantage such as reliable semiconductor device integration.
Regarding claim 18. WANG and Meyer disclose the semiconductor chip of claim 17, WANG further disclose wherein the conductive bumps comprise copper pillars (Para [ 0028]).
Regarding claim 19. WANG and Meyer disclose the semiconductor chip of claim 16, WANG further disclose wherein the corner portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a) has a varying thickness that gradually changes from the first thickness at the inner perimeter of the corner portion to the smaller second thickness at the edge of the corner portion (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
Regarding claim 20. WANG and Meyer disclose the semiconductor chip of claim 16, WANG further disclose wherein the corner portion of the semiconductor chip (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a) has a constant thickness, the constant thickness being the smaller second thickness (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a), and the semiconductor chip has a step-like thickness change at the inner perimeter of the corner portion from the smaller second thickness to the first thickness (Fig. [6], semiconductor die 100-1, Para [ 0064] includes corner region 401a).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over WANG et al (US 2022/0406752 A1; hereafter WANG) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of Malatkar et al (US 2017/0186705 A1; hereafter Malatkar).
Regarding claim 5. WANG and Meyer disclose the flip-chip assembly of claim 1, But WANG and Meyer do not disclose explicitly wherein a footprint of the corner portion on a main surface of the semiconductor chip has a polygonal shape.
In a similar field of endeavor, Malatkar discloses wherein a footprint of the corner portion on a main surface of the semiconductor chip has a polygonal shape (Fig [1], semiconductor device 10d, Para [0034-0038, 0065-0066]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Choi and Meyer in light of Malatkar teaching “wherein an inner perimeter of the corner portion has a shape of a circular or elliptical arc (Fig [8], semiconductor device 10d, Para [0038])” for further advantage such as improved I/O routing, improved reliability, and lower warpage during mounting of electronic components.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over WANG et al (US 2022/0406752 A1; hereafter WANG) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of Eom et al (US 2011/0089577 A1; hereafter Eom).
Regarding claim 7. WANG and Meyer disclose the flip-chip assembly of claim 1, But WANG and Meyer do not disclose explicitly wherein a bump of the plurality of conductive bumps comprises:
a cylindrical stub directly attached to the semiconductor chip;
a reflowed solder cap directly attached to the substrate; and a barrier layer sandwiched between the cylindrical stub and the reflowed solder cap.
In a similar field of endeavor, Eom discloses wherein a bump of the plurality of conductive bumps comprises:
a cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) directly attached to the semiconductor chip (Fig 1, substrate 30);
a reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032]) directly attached to the substrate (Fig 1, substrate 30, Para [ 0030-0032]); and a barrier layer (solder 14, Para [ 0030-0032]) sandwiched between the cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) and the reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG and Meyer in light of Eom teaching “a cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) directly attached to the semiconductor chip (Fig 1, substrate 30); a reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032]) directly attached to the substrate (Fig 1, substrate 30, Para [ 0030-0032]); and a barrier layer (solder 14, Para [ 0030-0032]) sandwiched between the cylindrical stub (Fig 1, electrode 32, Para [ 0030-0032]) and the reflowed solder cap (Fig 1, electrode 12, Para [ 0030-0032])” for further advantage such as bonding a flip chip while increasing the manufacturing yield.
Claim 8 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over WANG et al (US 2022/0406752 A1; hereafter WANG) in view of Meyer et al (US 2014/0197530 A1; hereafter Meyer) as applied claims above and further in view of IWAI et al (US 2021/0066238 A1; hereafter IWAI).
Regarding claim 8. WANG and Meyer disclose the flip-chip assembly of claim 1, But WANG and Meyer do not disclose explicitly wherein a difference between the first thickness and the smaller second thickness is in a range between 0.02 mm and 0.2 mm.
In a similar field of endeavor, IWAI discloses wherein a difference between the first thickness and the smaller second thickness is in a range between 0.02 mm and 0.2 mm (Fig [9], semiconductor device 10, Para [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG and Meyer in light of IWAI teaching “wherein a difference between the first thickness and the smaller second thickness is in a range between 0.02 mm and 0.2 mm (Fig [9], semiconductor device 10, Para [0069-0070])” for further advantage such as improved I/O routing, improved reliability, and lower warpage during mounting of electronic components.
Regarding claim 21. WANG and Meyer disclose the semiconductor chip of claim 16, But WANG and Meyer do not disclose explicitly wherein the second set of conductive bumps includes two or more bumps for which a vertical projection onto the semiconductor chip is fully between the inner perimeter of the corner portion and the edge of the corner portion.
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In a similar field of endeavor, IWAI discloses wherein the second set of conductive bumps includes two or more bumps for which a vertical projection onto the semiconductor chip is fully between the inner perimeter of the corner portion and the edge of the corner portion (Fig [17], TFT substrate 100 and IC 10, Para [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG and Meyer in light of IWAI teaching “wherein the second set of conductive bumps includes two or more bumps for which a vertical projection onto the semiconductor chip is fully between the inner perimeter of the corner portion and the edge of the corner portion (Fig [17], TFT substrate 100 and IC 10, Para [0069-0070])” for further advantage such as improved I/O routing, improved reliability, and lower warpage during mounting of electronic components.
Regarding claim 22. WANG and Meyer disclose the flip-chip assembly of claim 1, But WANG and Meyer do not disclose explicitly wherein the second set includes two or more bumps for which a vertical projection onto the semiconductor chip is fully between the inner perimeter of the corner portion and the edge of the corner portion.
In a similar field of endeavor, IWAI discloses wherein the second set of conductive bumps includes two or more bumps for which a vertical projection onto the semiconductor chip is fully between the inner perimeter of the corner portion and the edge of the corner portion (Fig [17], TFT substrate 100 and IC 10, Para [0069-0070]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine WANG and Meyer in light of IWAI teaching “wherein the second set of conductive bumps includes two or more bumps for which a vertical projection onto the semiconductor chip is fully between the inner perimeter of the corner portion and the edge of the corner portion (Fig [17], TFT substrate 100 and IC 10, Para [0069-0070])” for further advantage such as improved I/O routing, improved reliability, and lower warpage during mounting of electronic components.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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