DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 11/3/2025 is acknowledged.
Claims 1-4 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/3/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US PG Pub 2022/0189906, hereinafter Kim) in view of Lamson et al. (US PG Pub 2002/0089069, hereinafter Lamson).
Regarding claim 5, figures 1A-2C and 4A-4B of Kim disclose a method for assembling a semiconductor device, the method comprising:
bonding segments of a bond wire (123) between a vertical stack of semiconductor dies (110) and a first main surface of a substrate (100), the segments of the bond wire providing electrical connections between the semiconductor dies and the substrate, the vertical stack being supported on the first main surface of the substrate and having the semiconductor dies thereof horizontally offset with respect to one another; and
encapsulating, with a molding compound (130, ¶ 67), the vertical stack of semiconductor dies, the segments of the bond wire (123) attached between the vertical stack of semiconductor dies and the first main surface of the substrate, and at least a portion of the first main surface of the substrate (100).
Kim does not explicitly disclose coating a selected subset of the segments of the bond wire with an electrically insulating polymer.
In the same field of endeavor, figures 4a-4c of Lamson disclose coating a selected subset of the segments of a bond wire (41) with an electrically insulating polymer (45, ¶ 30-32).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to coat a selected subset of the segments of the bond wire with an electrically insulating polymer as taught by Lamson for the purpose of minimizing capacitance coupling between wires and thus improve reliability and performance of circuits (¶ 6).
Regarding claim 6, Lamson disclose selecting said selected subset of the segments of the bond wire based a bond-wire pitch in a corresponding part of the semiconductor device (¶ 6, coating is to minimize capacitance issues between neighboring wires..
Regarding claim 7, figure 1A of Kim discloses attaching a plurality of solder balls (140, ¶ 32) to the second main surface of the substrate (100).
Regarding claim 8, figures 1A-2C and 4A-4B of Kim in view of Lamson disclose a semiconductor device, comprising:
a substrate (100) having a first main surface and an opposing second main surface;
one or more semiconductor dies (110) attached to the first main surface;
a plurality of bond wires (123) electrically connecting at least one of the one or more semiconductor dies to the first main surface of the substrate, and
a molding compound (130, ¶ 67) encapsulating the one or more semiconductor dies, the plurality of bond wires, and at least a portion of the first main surface of the substrate.
Kim does not explicitly disclose one or more of the plurality of bond wires have been selectively coated with a polymer.
In the same field of endeavor, figures 4a-4c of Lamson disclose coating a selected subset of the segments of a bond wire (41) with an electrically insulating polymer (45, ¶ 30-32).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to coat one or more of the plurality of bond wire with an electrically insulating polymer as taught by Lamson for the purpose of minimizing capacitance coupling between wires and thus improve reliability and performance of circuits (¶ 6).
Regarding claim 9, figure 1A of Kim in view of Lamson discloses the entire claimed invention as noted in the above rejection of claim 7.
Regarding claim 10, figure 2C of Kim discloses the plurality of bond wires includes a first bond wire (123-1) and a second bond wire (123-2) in physical contact with one another; and
wherein at least one of the first bond wire and the second bond wire has one or more polymer coats in an area of the physical contact (see Lamson and rejection of claim 5).
Regarding claim 11, figure 2C of Kim discloses the first bond wire (123-1) has a first loop height; and
wherein the second bond wire (123-2) has a second loop height different from the first loop height.
Regarding claim 14, figure 2C of Kim discloses the first bond wire (123-1) and the second bond (123-2) wire have different respective loop shapes.
Regarding claim 15, figure 2C of Kim discloses the first bond wire (123-1) and the second bond wire (123-2) have different respective lengths.
Regarding claim 16, figure 1B of Kim discloses the plurality of bond wires includes a third bond wire and a fourth bond wire (additional wires that are spaced apart in the second direction) in another physical contact with one another; and wherein at least one of the third bond wire and the fourth bond wire has another polymer coat in an area of said another physical contact (Lamson and rejection of claim 5 above).
Regarding claims 17-18, Lamson discloses a polymer coat of the one or more polymer-coated bond wires comprises a thermosetting polymer (i.e. polyimide)(¶ 32).
Regarding claim 19, Lamson discloses a polymer coat of the one or more polymer-coated bond wires comprises a first dielectric material (polyimide, ¶ 32).; and
Kim discloses the molding compound (130) comprises a different second dielectric material (EMC, ¶ 31).
Regarding claim 20, figure 2C of Kim discloses the semiconductor dies (110) are arranged in a vertical stack attached to the first main surface and are horizontally offset with respect to one another.
Claims 10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (alternative interpretation, hereinafter Kim-2) in view of Lamson.
Regarding claim 10, figure 1B of Kim discloses the plurality of bond wires includes a first bond wire (leftmost 120) and a second bond wire (120 second from the left); and
wherein at least one of the first bond wire and the second bond wire has one or more polymer coats in an area of the physical contact (see Lamson and rejection of claim 5).
Kim does not explicitly disclose the first and second bond wires in physical contact with one another.
However, it’s obvious that during the molding process, the first and second wires may get deformed due to the mold flow and end up in physical contact with one another. This is confirmed by applicant’s specification to be a possible outcome of the molding process.
Regarding claim 12, figure 1B of Kim discloses the first bond wire (leftmost 120) is connected between a first contact pad located on a first one of the semiconductor dies (110) and a second contact pad located on the first main surface of the substrate; and
wherein the second bond wire (120 second from the left) is connected between a third contact pad located on one of the semiconductor dies and a fourth contact pad located on the first main surface of the substrate.
Regarding claim 13, figure 1B of Kim discloses the first bond wire (leftmost 120) is connected between a first contact pad located on a first semiconductor die (110) of the one or more semiconductor dies and a second contact pad located on the first main surface of the substrate; and
wherein the second bond wire (120 second from the left) is connected between a third contact pad located on the first semiconductor die and a fourth contact pad located on the first main surface of the substrate.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817