DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Specification 3
III. Claim Objections 3
IV. Claim Rejections - 35 USC § 112 4
A. Claims 1-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 4
1. Claims 1, 9, 11, and 18 4
2. Claim 15 5
V. Claim Rejections - 35 USC § 103 6
A. Claims 1, 2, 4-9, 11, and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0066887 (“Imai”). 6
B. Claims 1, 2, 4-9, 11, and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of US 2019/0326432 (“Nakazawa”). 20
C. Claims 6-9 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Imai or Imai in view of Nakazawa, as applied to claims 1 and 11 above, and further in view of US 2012/0313139 (“Matsuura”). 21
VI. Allowable Subject Matter 22
VII. Pertinent Prior Art 23
Conclusion 23
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Specification
The disclosure is objected to because of the following informalities:
The term “pass over” is misused throughout the specification for the reasons explained in the rejection of the claims under 35 USC 112(b), below. As explained below, it appears that Applicant means, instead, “pass under” or more specifically, “pass under and does not substantially contact” in the context of the claim limitations. Whatever amendment is made to the claims should be equally made in the specification.
Appropriate correction is required.
III. Claim Objections
Claims 1, 11, and 18 are objected to because of the following informalities:
In (1) claim 1 at p. 2, line 25 to p. 3, line 2 and (2) claim 11, at p. 10, lines 5-7, replace,
the first trench and the second trench are separate apart from so as to the second side surface and the third side surface are adjacent each other,
with, e.g., the following for clarity,
the first trench and the second trench are spaced apart such that the second side surface and the third side surface are adjacent each other,
Claims 9 and 18 also includes the phrase “separate apart from so as to” (p. 8 of claims at lines 2-4 and p. 14 of claims at lines 23-25) and should be amended as suggested for claims 1 and 11, above.
Appropriate correction is required.
IV. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 1-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
1. Claims 1, 9, 11, and 18
Claim 1 recites the following limitations:
forming a first gate insulating film on a side surface of the first trench and forming a second gate insulating film on a side surface of the second trench;
the first trench has a first side surface, a second side surface …
the second trench has a third side surface, a fourth side surface …
Each of the first, second, third and fourth side surfaces has an unclear antecedent basis because of each of the first and second trenches are previously required in the claim to have “a side surface”.
Claim 11 recites the same features as above and is indefinite for the same reason.
Each of claims 9 and 18 has essentially the same indefiniteness by unclear antecedent basis as claim 1 arising from first reciting “a side surface of the … trench” in the claims and then subsequently requiring the same trench to have two enumerated side surfaces.
Claim 1 also recites the following limitations:
the first impurity region is formed in the semiconductor substrate close to the first side surface [of the first trench] and covers the first bottom surface [of the first trench] so as to pass over the second side surface [of the first trench],
the second impurity region is formed in the semiconductor substrate close to the fourth side surface [of the second trench] and covers the second bottom surface [of the second trench] so as to pass over the third side surface [of the second trench],
It is unclear what is meant by “pass over” in the context of the second and third side surfaces of the first and second trenches, respectively. As shown in Figs. 10-12 of the Instant Application, the first and second impurity regions refer to the p-type floating regions PF. However the floating regions PF do not “pass over” the side surfaces of the trenches but, instead, pass under the trenches themselves as wells as the second and third side surfaces of the first and second trenches, respectively.
As best understood, Examiner presumes that, while Figs. 10-12 show that there is a small amount of contact of the floating regions PF with the second and third side surfaces of the first and second trenches, respectively, that the floating regions PF do not contact the majority of the second and third side surfaces of the first and second trenches, respectively. For the purposes of examination, this claim limitation will be interpreted based on the presumption just explained, i.e. “so as to pass under and not substantially contact the second(third) side surface”.
Each of claims 9, 11, and 18 also misuses the term “pass over” in the same way as in claim 1 and is, consequently, indefinite for this additional reason.
The remaining listed claims, as well as claims 9 and 18, are rejected for including the same indefinite limitations by depending from one of claims 1 and 11 either directly or indirectly.
2. Claim 15
Claim 15 recites the limitation “the first resist pattern” in step (g3). This limitation lacks antecedent basis in the claim. Inasmuch as claim 15 forms a single impurity region, i.e. the “third impurity region” —although not claimed, the hole blocking region NHB—by two implantation steps as different energies, it is presumed that the limitation is, instead, “the second resist pattern” for which there is antecedent basis in the claim.
Claims 16-19 are rejected for including the same indefinite feature by depending from claim 15 either directly or indirectly.
V. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 2, 4-9, 11, and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0066887 (“Imai”).
With regard to claim 11, Imai discloses,
11. A manufacturing method of a semiconductor device [an IGBT; abstract, Figs. 1-3] comprising the steps of:
(a) preparing a semiconductor substrate SB of a first conductivity type [n-type] having an upper surface and a bottom surface opposite to the upper surface [¶ 92; Fig. 5];
(b) after the step of (a), forming a first ion-implantation layer [left PF in Fig. 5] and a second ion-implantation layer [center PF in Fig. 5] in the semiconductor substrate by performing a first ion-implantation [¶ 94];
(c) after the step of (b), by performing a first heat treatment for the semiconductor substrate SB, forming a first impurity region [left PF in Fig. 7] of a second conductivity type [p-type from boron implantation (¶ 94)] opposite to the first conductivity type [n-type] by diffusing impurities included in the first ion-implantation layer [left PF in Fig. 5] and forming a second impurity region [center PF in Fig. 7] of the second conductivity type [p-type from boron implantation (¶ 94)] by diffusing impurities included in the second ion-implantation layer [center PF in Fig. 5];
(d) … forming a first trench [left trench T1 in Fig. 6] and a second trench [right trench T1 from left in Fig. 6] on the upper surface of the semiconductor substrate SB [¶¶ 95-97];
(e) after the step of (d), forming a first gate insulating film GF on a side surface of the first trench [left T1] and forming a second gate insulating film GF on a side surface of the second trench [right T1] [¶¶ 99-100; Fig. 7]; and
(f) after the step of (e), forming a first gate electrode [left G1] so as to fill in the first trench [left T1] via the first gate insulating film GF and forming a second gate electrode [right G1] so as to fill in the second trench [right T1] via the second gate insulating film GF [¶¶ 101-104; Figs. 8-9],
wherein
[1] the first trench [left T1] has a first side surface [left side of left T1], a second side surface [right side of left T1] facing to the first side surface and a first bottom surface connecting the first side surface and the second side surface [as shown in Figs. 6-9],
[2] the second trench [right T1] has a third side surface [left side of right T1], a fourth side surface [right side of right T1] facing to the third side surface and a second bottom surface connecting the third side surface and the fourth side surface [as shown in Figs. 6-9],
[3] the first trench [left T1] and the second trench [right T1] are separate apart from so as to the second side surface and the third side surface are adjacent each other [as shown in Figs. 6-9],
[4] the first impurity region [left PF] is formed in the semiconductor substrate SB close to the first side surface [left side of left T1] and covers the first bottom surface [of left T1] so as to pass over [i.e. not contact] the second side surface [right side of left T1] [as shown in Figs. 7-9],
[5] the second impurity region [center PF] is formed in the semiconductor substrate SB close to the fourth side surface [right side of right T1] and covers the second bottom surface so as to pass over [i.e. not contact] the third side surface [left side of right T1] [as shown in Figs. 7-9], and
[6] the first impurity region [left PF] and the second impurity region [center PF] are separate apart from each other [as shown in Figs. 7-9].
With regard to step (d) of claim 11, Imai does not disclose that the etching of the first and second trenches is performed after the first heat treatment of claimed step (c), as required by step (d). However, it has been held that the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946).
This is all of the features of claim 11.
With regard to claim 13, Imai further discloses,
13. The manufacturing method of the semiconductor device according to claim 11, wherein
[1] in the step of (e), a silicon oxide film is formed by thermal oxidation method [¶ 100], the first gate insulating film GF and the second gate insulating film GF are included the silicon oxide film, and
[2] in the step of (c), the first heat treatment is performed [¶ 99] at lower temperature and shorter time than a heat treatment performed by thermal oxidation method [¶ 100].
Imai states,
[0099] First, heat treatment is performed on the semiconductor substrate SB to diffuse the impurity contained in the hole barrier region NHB and the floating region PF. By this heat treatment, the hole barrier region NHB diffuses to a position near the bottom of each of the trenches T1 and T2, and the floating region PF diffuses to a position deeper than the bottom of each of the trenches T1 and T2 so as to cover the bottom of each of the trenches T1 and T2.
[0100] Note that in the case where the above-described ion implantation is performed a plurality of times, since the hole barrier region NHB and the floating region PF have already been formed to a deep position, this heat treatment step can be omitted or the time of the heat treatment step can be shortened. Next, a thermal oxidation process is performed on the semiconductor substrate SB, whereby a gate dielectric film GF made of, for example, a silicon oxide film is formed on the inner wall of the trench T1, the inner wall of the trench T2, the upper surface of the floating region PF, and the upper surface of the hole barrier region NHB. The thickness of the gate dielectric film GF is, for example, 100 nm.
(Imai: ¶¶ 99-100; emphasis added)
Inasmuch as the heat treatment for diffusing the p-type impurities of the PF region can be omitted or shortened, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, perform “the first [i.e. diffusion] heat treatment … at lower temperature and shorter time than a heat treatment performed by thermal oxidation method”, because (1) Imai teaches that the plural implantations can even eliminate the need for the heat treatment (id.) and (2) it would reduce the thermal budget, which is known to be beneficial by one having ordinary skill in the art.
Claim 14 reads,
14. The manufacturing method of the semiconductor device according to claim 11, wherein the first heat treatment is performed at a temperature of 700 to 900 degree Celsius with a process time of 30 to 150 seconds.
The selection of the “temperature of 700 to 900 degree Celsius with a process time of 30 to 150 seconds” is obvious because it is a matter of determining optimum process condition by routine experimentation with a limited number of species. See In re Jones, 162 USPQ 224 (CCPA 1955)(the selection of optimum ranges within prior art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980)(discovery of optimum value of result effective variable in a known process is obvious).
With regard to claim 15, Imai further discloses,
15. The manufacturing method of the semiconductor device according to claim 11, after the step of (a) before the step of (b) or after the step of (b) before the step of (c),
(g1) forming a second resist pattern [not shown] on the upper surface of the semiconductor substrate SB [¶ 93; see explanation below]
(g2) after the step of (g1), forming a fifth ion-implantation layer NHB in the semiconductor substrate SB by performing a third ion-implantation with a third ion-implantation energy by using the second resist pattern [not shown] as a mask [¶ 94; Fig. 5; see explanation below];
(g3) after the step of (g2), forming a sixth ion-implantation layer NHB at a position overlapping the fifth ion-implantation layer in the semiconductor substrate SB in plan view by performing a fourth ion-implantation with a fourth ion-implantation energy different of the third ion-implantation energy by using the first [sic; should be “second”] resist pattern [not shown] as a mask [¶ 94; Fig. 5; see explanation below]; and
(g4) after the step of (g3), removing the second resist pattern [as shown in Fig. 5],
wherein
[1] in the step of (c), by performing the first heat treatment for the semiconductor substrate, forming a third impurity region NHB of the first conductivity type [n-type] by diffusing impurities included in the fifth ion-implantation layer NHB and the sixth ion-implantation layer NHB [¶ 94; see explanation below]; and
[2] the third impurity region NHB is formed in the semiconductor substrate SB between the second side surface [right side of left T1] and the third side surface [left side of right T1] [as shown in Figs. 7-9].
With regard to step (g1), Imai does not show first and second resist patterns for implanting each of the p-type impurities for the p-type floating regions PF and the n-type impurities for the n-type hole block layer NHB. However, Imai states, “an n-type hole barrier region NHB and a p-type floating region PF are formed on the surface of the drift region NV by photolithography and ion implantation.” (¶ 93) Photolithography necessarily requires a photoresist that is patterned by exposure to light through a patterned mask and then developed to leave openings in the resist, as is known to one having ordinary skill in the art. Therefore it is held, absent evidence to the contrary, that Imai inherently uses first and second resist patterns to perform the separate n-type and p-type ion implantation steps for forming the NHB and PF regions, explained in paragraph [0094]—especially since the n-type and p-type dopants cannot be implanted at the same time. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to steps (g2) and (g3) and feature [1] of claim 15, Imai states,
[0094] The impurity for forming the hole barrier region NHB is, for example, phosphorus (P), and the ion implantation is performed under the condition that the dose is about 5×10 12 per cm 2 to 2×10 13 per cm 2 and the energy is 300 keV or more. The ion implantation may be performed in a plurality of times, and in this case, the ion implantation is performed within a range of 500 to 2500 keV. The impurity for forming the floating regions PF is boron (B), for example, and the ion implantation is performed under the condition that the dose is about 4×10 13 per cm 2 and the energy is 75 keV or more. The ion implantation may be performed in a plurality of times, and in this case, the ion implantation is performed within a range of 200 to 1500 keV.
[0100] Note that in the case where the above-described ion implantation is performed a plurality of times, since the hole barrier region NHB and the floating region PF have already been formed to a deep position, this heat treatment step can be omitted or the time of the heat treatment step can be shortened.
(Imai: ¶ 94; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use plural implantation steps at different energies (1) because Imai suggests this (¶ 94) and (2) in order to form the NHB region from the top surface to the desired depth with more control over the doping profile and (3) in order to reduce the time required for the diffusing heat treatment step, as suggested by Imai (¶ 100).
This is all of the features of claim 15.
Claim 16 reads,
16. The manufacturing method of the semiconductor device according to claim 15, wherein the third ion-implantation energy is larger than the fourth ion-implantation energy.
Although Imai does not indicate that an ion implantation of larger energy is performed before an ion implantation of lower energy, again, the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. See In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). There is no evidence of unexpected results.
With regard to claim 17, Imai further discloses,
17. The manufacturing method of the semiconductor device according to claim 16, further comprising the steps of:
(h) after the step of (f), forming a base region PB of the second conductivity type [p-type] in the third impurity region close to the upper surface of the semiconductor substrate SB so as to be shallower than the first bottom surface of the first trench [left T1] and the second bottom surface of the second trench [right T1] [¶¶ 105-106; Fig. 10];
(i) after the step of (h), forming an emitter region NE of the first conductivity type n-type] in the base region PB [¶ 107; Fig. 10];
(j) after the step of (i), forming an interlayer insulating film IL1 and/or IL2 on the upper surface of the semiconductor substrate SB so as to cover the first trench [left T1] and the second trench [right T1] [¶¶ 108, 112; Figs. 11-13];
(k) after the step of (j), forming a gate wiring GE [Fig. 1; ¶ 54] and an emitter electrode EE on the interlayer insulating film IL1 and/or IL2 [¶¶ 118-120; Figs. 1 and 15];
(l) after the step of (k), forming a collector region PC of the second conductivity type [p-type] in the semiconductor substrate SB close to the bottom surface of the semiconductor substrate SB [¶¶ 121-122; Fig. 3]; and
(m) after the step of (l), forming a collector electrode CE on the bottom surface of the semiconductor substrate SB [¶ 123; Fig. 3],
wherein
[1] the emitter region NE and the base region PB are electrically connected to the emitter electrode EE [as shown in Fig. 15],
[2] the first gate electrode [left G1 in Figs. 3 and 15] and the second gate electrode [right G1 in Figs. 3 and 15] are electrically connected to the gate wiring GE [¶ 54: “Although not shown, the gate electrode G1 is electrically connected to the gate potential electrode GE shown in FIG. 1, and a gate potential is applied to the gate electrode G1 during the operation of the IGBT.”]; and
[3] the collector region PC is electrically connected to the collector electrode CE [¶ 121; Fig. 3].
With regard to claim 18, Imai further discloses,
18. The manufacturing method of the semiconductor device according to claim 17, wherein
[1] in the step of (b), forming a seventh ion-implantation layer [right PF in Fig. 5] in the semiconductor substrate SB by performing the first ion-implantation [¶ 94];
[2] in the step of (c), by performing the first heat treatment, forming a fourth impurity region [left PF in Fig. 7] of the second conductivity type [p-type from boron implantation (¶ 94)] by diffusing impurities included in the seventh ion-implantation layer;
[3] in the step of (d), forming a third trench [left T2 in Fig. 6] and a fourth trench [right T2 in Fig. 6] on the upper surface of the semiconductor substrate SB [¶¶ 95-97];
[4] in the step of (e), forming a third gate insulating film GF on a side surface of the third trench [left T2] and forming a fourth gate insulating film GF on a side surface of the fourth trench [right T2] [¶¶ 99-100; Fig. 7]; and
[5] in the step of (f), forming a third gate electrode [left G2] so as to fill in the third trench via [left T2] the third gate insulating film GF and forming a fourth gate electrode [right G2] so as to fill in the fourth trench [right T2] via the fourth gate insulating film GF [¶¶ 101-104; Figs. 8-9],
wherein
[6] the third trench [left T2] has a fifth side surface [left side of left T2], a sixth side surface [right side of left T2] facing to the fifth side surface and a third bottom surface connecting the fifth side surface and the sixth side surface,
[7] the fourth trench [right T2] has a seventh side surface [left side of right T2], an eighth side surface [right side of right T2] facing to the seventh side surface and a fourth bottom surface connecting the seventh side surface and the eighth side surface,
[8] the third trench [left T2] and the fourth trench [right T2] are separate apart from so as to the sixth side surface [right side of left T2] and the seventh side surface [left side of right T2] are adjacent each other [as shown in Figs. 7-9],
[9] the second impurity region [center PF in Figs. 7-9] is formed in the semiconductor substrate SB between the fourth side surface [right side of right T1] and the fifth side surface [left side of left T2] and covers the third bottom surface [of left T2] so as to pass over the sixth side surface [right side of left T2],
[10] the fourth impurity region [right PF in Fig. 7-9] is formed in the semiconductor substrate SB close to the eighth side surface [right side of right T2] and covers the fourth bottom surface [of left T2] so as to pass over [i.e. not contact] the seventh side surface [left side of right T2],
[11] the interlayer insulating film IL1 and/or IL2 is formed so as to cover the third trench [left T2] and the fourth trench [right T2], and
[12] the third gate electrode [left G2] and the fourth gate electrode [right G2] are electrically connected to the emitter electrode EE [as shown in Figs. 3 and 15].
Claim 1 reads,
1. A manufacturing method of a semiconductor device comprising the steps of:
(a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a bottom surface opposite to the upper surface;
(b) after the step of (a), forming a first resist pattern on the upper surface of the semiconductor substrate;
(c) after the step of (b), forming a first ion-implantation layer and a second ion-implantation layer in the semiconductor substrate by performing a first ion-implantation with a first ion-implantation energy by using the first resist pattern as a mask;
(d) after the step of (c), forming a third ion-implantation layer at a position overlapping the first ion-implantation layer in the semiconductor substrate in plan view and forming a fourth ion-implantation layer at a position overlapping the second ion-implantation layer in the semiconductor substrate in plan view by performing a second ion-implantation with a second ion-implantation energy different of the first ion-implantation energy by using the first resist pattern as a mask;
(e) after the step of (d), removing the first resist pattern;
(f) after the step of (e), by performing a first heat treatment for the semiconductor substrate, forming a first impurity region of a second conductivity type opposite to the first conductivity type by diffusing impurities included in the first ion-implantation layer and the third ion-implantation layer and forming a second impurity region of the second conductivity type by diffusing impurities included in the second ion-implantation layer and the fourth ion-implantation layer;
(g) after the step of (f), forming a first trench and a second trench on the upper surface of the semiconductor substrate;
(h) after the step of (g), forming a first gate insulating film on a side surface of the first trench and forming a second gate insulating film on a side surface of the second trench; and
(i) after the step of (h), forming a first gate electrode so as to fill in the first trench via the first gate insulating film and forming a second gate electrode so as to fill in the second trench via the second gate insulating film,
wherein
[1] the first trench has a first side surface, a second side surface facing to the first side surface and a first bottom surface connecting the first side surface and the second side surface,
[2] the second trench has a third side surface, a fourth side surface facing to the third side surface and a second bottom surface connecting the third side surface and the fourth side surface,
[3] the first trench and the second trench are separate apart from so as to the second side surface and the third side surface are adjacent each other,
[4] the first impurity region is formed in the semiconductor substrate close to the first side surface and covers the first bottom surface so as to pass over the second side surface,
[5] the second impurity region is formed in the semiconductor substrate close to the fourth side surface and covers the second bottom surface so as to pass over the third side surface, and
[6] the first impurity region and the second impurity region are separate apart from each other.
Claim 1 is distinguished from claim 11 in additionally requiring (1) forming of a first resist pattern in step (d), (2) performing two implantation steps using the resist pattern as a mask in step (d) that subsequently form the first and second impurity regions by the heat treatment in step (f), and (3) removal of the first photoresist pattern in step (e).
The use of the photoresist pattern including its used and subsequent removal after implantation is inherent for the implantation of the first and second PF regions in Imai for the same reasons as explained under claim 15, which is incorporated here. In addition, the use of plural implantations steps of different energies to form the PF regions is (1) explicitly suggested in paragraphs [0094] and [0100] of Imai quoted above and (2) obvious for the same reasons as explained under claim 15, which are incorporated here.
To effectively repeat from claim 15, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use plural implantation steps at different energies (1) because Imai suggests this (¶ 94) and (2) in order to form the PF regions from the top surface to the desired depth with more control over the doping profile and (3) in order to reduce the time required for the diffusing heat treatment step, as suggested by Imai (¶ 100).
This all of the features of claim 1 have been addressed above under claims 1 and 15.
Claim 2 reads,
2. The manufacturing method of the semiconductor device according to claim 1, wherein the first ion-implantation energy is larger than the second ion-implantation energy.
See discussion under claim 1.
Claims 4 and 5 read,
4. The manufacturing method of the semiconductor device according to claim 1, wherein in the step of (h), a silicon oxide film is formed by thermal oxidation method, the first gate insulating film and the second gate insulating film are included the silicon oxide film, and in the step of (f), the first heat treatment is performed at lower temperature and shorter time than a heat treatment performed by thermal oxidation method.
5. The manufacturing method of the semiconductor device according to claim 1, wherein the first heat treatment is performed at a temperature of 700 to 900 degree Celsius with a process time of 30 to 150 seconds.
See discussions under claims 13 and 14, respectively, which are incorporated here.
Claims 6 and 7 read,
6. The manufacturing method of the semiconductor device according to claim 2, after the step of (a) before the step of (b) or after the step of (e) before the step of (f),
(j1) forming a second resist pattern on the upper surface of the semiconductor substrate;
(j2) after the step of (j1), forming a fifth ion-implantation layer in the semiconductor substrate by performing a third ion-implantation with a third ion-implantation energy by using the second resist pattern as a mask;
(j3) after the step of (j2), forming a sixth ion-implantation layer at a position overlapping the fifth ion-implantation layer in the semiconductor substrate in plan view by performing a fourth ion-implantation with a fourth ion-implantation energy different of the third ion-implantation energy by using the first resist pattern as a mask; and
(j4) after the step of (j3), removing the second resist pattern,
wherein
[1] in the step of (f), by performing the first heat treatment for the semiconductor substrate, forming a third impurity region of the first conductivity type by diffusing impurities included in the fifth ion-implantation layer and the sixth ion-implantation layer; and
[2] the third impurity region is formed in the semiconductor substrate between the second side surface and the third side surface.
7. The manufacturing method of the semiconductor device according to claim 6, wherein the third ion-implantation energy is larger than the fourth ion-implantation energy.
See discussions under claims 15 and 16, respectively, which are incorporated here.
Claim 8 reads,
8. The manufacturing method of the semiconductor device according to claim 6, further comprising the steps of:
(k) after the step of (i), forming a base region of the second conductivity type in the third impurity region close to the upper surface of the semiconductor substrate so as to be shallower than the first bottom surface of the first trench and the second bottom surface of the second trench;
(l) after the step of (k), forming an emitter region of the first conductivity type in the base region;
(m) after the step of (l), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the first trench and the second trench;
(n) after the step of (m), forming a gate wiring and an emitter electrode on the interlayer insulating film;
(o) after the step of (n), forming a collector region of the second conductivity type in the semiconductor substrate close to the bottom surface of the semiconductor substrate; and
(p) after the step of (o), forming a collector electrode on the bottom surface of the semiconductor substrate,
wherein
[1] the emitter region and the base region are electrically connected to the emitter electrode,
[2] the first gate electrode and the second gate electrode are electrically connected to the gate wiring; and
[3] the collector region is electrically connected to the collector electrode.
See discussion under claim 17, which is incorporated here.
Claim 9 reads,
9. The manufacturing method of the semiconductor device according to claim 8, wherein
[1] in the step of (c), forming a seventh ion-implantation layer in the semiconductor substrate by performing the first ion-implantation;
[2] in the step of (d), forming an eighth ion-implantation layer at a position overlapping the seventh ion-implantation layer in the semiconductor substrate in plan view by performing the second ion-implantation;
[3] in the step of (f), by performing the first heat treatment, forming a fourth impurity region of the second conductivity type by diffusing impurities included in the seventh ion-implantation layer and the eighth ion-implantation layer;
[4] in the step of (g), forming a third trench and a fourth trench on the upper surface of the semiconductor substrate;
[5] in the step of (h), forming a third gate insulating film on a side surface of the third trench and forming a fourth gate insulating film on a side surface of the fourth trench;
[6] and in the step of (i), forming a third gate electrode so as to fill in the third trench via the third gate insulating film and forming a fourth gate electrode so as to fill in the fourth trench via the fourth gate insulating film,
wherein
[7] the third trench has a fifth side surface, a sixth side surface facing to the fifth side surface and a third bottom surface connecting the fifth side surface and the sixth side surface,
[8] the fourth trench has a seventh side surface, an eighth side surface facing to the seventh side surface and a fourth bottom surface connecting the seventh side surface and the eighth side surface,
[9] the third trench and the fourth trench are separate apart from so as to the sixth side surface and the seventh side surface are adjacent each other,
[10] the second impurity region is formed in the semiconductor substrate between the fourth side surface and the fifth side surface and covers the third bottom surface so as to pass over the sixth side surface,
[11] the fourth impurity region is formed in the semiconductor substrate close to the eighth side surface and covers the fourth bottom surface so as to pass over the seventh side surface,
[12] the interlayer insulating film is formed so as to cover the third trench and the fourth trench, and
[13] the third gate electrode and the fourth gate electrode are electrically connected to the emitter electrode.
See discussion under claim 18 which is incorporated here, as well as the discussion under claim 1 directed to the multiple implantation steps as it applies the eighth implantation layer in steps (d) and (f) in claim 18.
B. Claims 1, 2, 4-9, 11, and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of US 2019/0326432 (“Nakazawa”).
As explained above, Imai discloses each of the limitations of independent claims 1 and 11 except for performing the claimed trench etching of step (g) of claim 1 or step (d) of claim 11 of after the claimed heat treatment to diffuse the implanted impurities to form the first and second impurity region, i.e. the p-type floating regions PF in step (f) of claim 1 and step (c) of claim 11.
Nakazawa, like Imai, teaches a process of forming an IGBT having pairs of gate electrodes GE on either side of an emitter region NE with first and second p-type floating regions PF adjacent to the outer side surfaces of the GE pairs (Nakazawa: Figs. 1, 6, 7). Nakazawa further teaches that the p-type dopant implantation and diffusion anneal (Nakazawa: Fig. 11; ¶ 105) are performed before the etching of the gate trenches TR1 (Fig. 13; ¶ 106).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to etch the gate electrode trenches in Imai after the implantation and annealing of the p-type floating regions PF because Nakazawa teaches that this sequence is not and results in the same PF floating regions and gate trenches.
Thus, to the extent that Applicant may provide evidence of unexpected results for the sequence of etching the gate electrode trenches after the implantation and annealing of the first and second impurity regions, Nakazawa still teaches that the claimed sequence is obvious.
This is all of the additional limitations of claims 1, 2, 4-9, 11, and 13-18.
C. Claims 6-9 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Imai or Imai in view of Nakazawa, as applied to claims 1 and 11 above, and further in view of US 2012/0313139 (“Matsuura”).
The prior art of Imai or Imai in view of Nakazawa, as explained above, teaches each of the features of claims 6 and 15. To the extent that Applicant may provide proof that the “photolithography and implantation” to form each of the HBL and PF regions does not require separate photoresist patterns—as point with which Examiner disagrees given the requirements of photolithography and implantation—then this would be a difference between claim 15 and Imai.
Matsuura, like Imai and Nakazawa, teaches a method of making an IGBT having each of p-type floating regions 16 on the outer and bottom sides of a pair of gate trenches and an n-type hole blocking layer 24 between the pair of trenches (Matsuura: Figs. 8-18; ¶¶ 138-142). Matsuura further teaches that a first photoresist pattern 31 is used to implant the n-type impurities for the hole blocking implantation layer 24 that become the hole blocking region 24 upon annealing (Figs. 9 and 16) and a second photoresist pattern 32 is used to implant each of the p-type floating implantation layers 16 that become the p-type floating regions 16 (Figs. 10 and 16; Matsuura: ¶¶ 148-149, 155).
Thus, to the extent that the “photolithography and implantation” to form each of the HBL and PF regions in Imai may not be inherent, then it would have been at least obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use separate photoresist patterns, because Matsuura teaches that it is known in the art to use “normal lithography” of resist layers to form resist patterns for forming the identical PF and NHB regions in an IGBT.
This is all of the additional features of claims 6-9 and 15-18.
VI. Allowable Subject Matter
Pending overcoming the rejection under 35 USC 112(b), claims 3, 10, 12, and 19 would be objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 3 and 12 read,
3. The manufacturing method of the semiconductor device according to claim 2, in the step of (g), forming the first trench and the second trench so as to be positions of each of the first bottom surface and the second bottom surface shallower than peak positions of an impurity concentration of each of the first ion-implantation layer and the second ion-implantation layer.
12. The manufacturing method of the semiconductor device according to claim 11, in the step of (d), forming the first trench and the second trench so as to be positions of each of the first bottom surface and the second bottom surface shallower than peak positions of an impurity concentration of each of the first ion-implantation layer and the second ion-implantation layer.
The prior art does not reasonably teach or suggest—in the context of the claims—the limitation recited in claims 3 and 12.
Claims 10 and 19 read,
10. The manufacturing method of the semiconductor device according to claim 9, wherein the second impurity region and the fourth impurity region are in contact with each other.
19. The manufacturing method of the semiconductor device according to claim 18, wherein the second impurity region and the fourth impurity region are in contact with each other.
The prior art does not reasonably teach or suggest—in the context of the claims—the limitation recited in claims 10 and 19.
VII. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2015/0340480 (“Matsuura”) is cited for teaching a feature similar to claims 10 and 19 by showing a p-type region PCO that connects the two separate p-type floating regions PF formed on the outside surfaces and bottom surfaces of a pair of adjacent gate electrodes GI (Matsuura: Fig. 34). However, this is a separate region from the otherwise separate PF regions and therefore does not read on the claim limitation “the second impurity region and the fourth impurity region are in contact with each other.”
US 2013/0175574 (“Matsuura”) is cited for disclosed at least all of the features of claim 11.
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814