Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I: Claims 1-9 in the reply filed on 4/8/2026 is acknowledged.
Applicant’s traversal is unpersuasive. While Applicant argues that the groups "lack the same or corresponding special technical features," this Unity of Invention standard (MPEP 1800) does not apply to the present application. As indicated in the Application Data Sheet (ADS) filed 08/15/2023, this is a Continuation filed under 35 U.S.C. 111(a); therefore, the restriction is governed by the "independent and distinct" criteria of 35 U.S.C. 121.
Furthermore, the Examiner appreciates Applicant’s technical explanation that the stack "can be formed separately and subsequently transferred or placed onto the substrate." This specific alternative method provided by Applicant successfully demonstrates that the claimed product can be made by a materially different process than the one currently claimed, establishing distinctness under MPEP 806.05(f). Accordingly, the restriction is maintained.
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected, there being no allowable generic or linking claim.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (US 20240040777 A1).
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CLAIM 1. Huang teaches a semiconductor structure, comprising:
a substrate (Huang - Abstract1 Note: substrate not shown in figures.); and
a stack structure located on the substrate (Abstract & Figs 1-2), the stack structure comprising a plurality of memory units arranged at intervals in a first direction (Stacking direction D2), each of the plurality of memory units comprising a transistor structure TR, the transistor structure comprising an active structure 20 and a gate layer 11, at least part of the active structure being distributed around a periphery of part of the gate layer (Figs. 1-2), a projection of the active structure on a top surface of the substrate being in a shape of a U which opens toward a second direction, wherein both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects with the second direction (Figs. 1-2).
Under the Broadest Reasonable Interpretation (BRI), the limitation of an active structure having a "projection... in a shape of a U which opens toward a second direction" is not restricted to a structure that is exclusively open-ended. A closed-loop or rectangular active structure (e.g., layer 20 of Huang) that surrounds a gate layer inherently comprises the claimed U-shaped geometry within its profile. Any three contiguous sides of such a structure necessarily form a U-shape that flanks the gate and defines an interior space opening toward the second direction. Because the claim uses the transition term "comprising," it does not exclude additional segments—such as a fourth side—that close the loop. Furthermore, this U-shaped geometry is oriented such that it opens toward the second direction, which encompasses an opening directed either toward the bit line (layer 17) or toward the capacitor structure, depending on the relative orientation of the concave portion of the channel to the associated electrical contacts. Therefore, the surrounding channel of the prior art meets the U-shape requirement as it encompasses the claimed geometry while oriented toward the specified functional components.
Allowable Subject Matter
Claim 2 and subsequent depending claims 3-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
The primary reason for the allowance of the claims is the inclusion of the limitation “a second gate layer, the second gate layer being distributed at least around a periphery of the part of the active structure, and the first gate layer being electrically connected to the second gate layer“, in all of the claims which is not found in the prior art references.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
4/20/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Abstract - A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; and a stack structure arranged on the substrate. The stack structure includes storage areas spaced apart from each other in a first direction, and isolation walls, each isolation wall being arranged between any two adjacent storage areas of the storage areas. Each storage area includes memory cells spaced apart from each other in a second direction, each memory cell including a transistor structure, and a capacitor structure, an outline of a projection of the capacitor structure on a top surface of the substrate being in a shape of a rectangle or a rounded rectangle. A width of the transistor structure is equal to a width of the capacitor structure in the first direction, and the transistor structure is aligned with the capacitor structure in the third direction.
Prosecution Insights